OMAPL137-HT Datasheet, PDF (237/444 Pages) Texas Instruments – Multimedia Device

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OMAP4460
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(2) Y = [31:0]
(3) Z = [9:0]
(4) CA1 = Bank A Row Address
(5) CA2 = Row Address
(6) CA3 = Bank B Row Address
(7) CA4 = Row Address
(8) CA5 = Bank A Column Address
(9) CA6 = Column Address
(10) CA7 = Bank A
SWPS046A – JANUARY 2012
Completion of Burst Write
lpddr2_ck
lpddr2_nck
lpddr2_caZ
[Cmd]
lpddr2_dqsX
lpddr2_ndqsX
lpddr2_dY
CA1 CA2
Write
CA3
Nop
Nop
Nop
Nop
Precharge
DD405_MAX
DD510
DOUT A0 DOUT A1 DOUT A2
DOUT A3
Nop
SWPS040-033
Figure 5-34. EMIF—DDR Mode—SDRAM Core Parameters—Write Recovery Time^{(1)(2)(3)(4)(5)(6)}
(1) X = [3:0]
(2) Y = [31:0]
(3) Z = [9:0]
(4) CA1 = Bank A Column Address A
(5) CA2 = Column Address
(6) CA3 = Bank A
Completion of Burst Write
lpddr2_ck
lpddr2_nck
lpddr2_caZ
CA1 CA2
CA3 CA4
[Cmd]
Write
Nop
Nop
Nop
Nop
Nop
Read
lpddr2_dqsX
lpddr2_ndqsX
lpddr2_dZ
DOUT A0 DOUT A1 DOUT A2
DOUT A3
DD606
DD511
SWPS040-034
Figure 5-35. EMIF—DDR Mode—SDRAM Core Parameters—Write to Read Command^{(1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)}
(1) X = [3:0]
(2) Y = [31:0]
(3) Z = [9:0]
(4) CA1[SDRAM DD511] = Bank M Column Address A
(5) CA2[SDRAM DD511] = Column Address A
Copyright © 2012, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 237
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