OMAPL137-HT Datasheet, PDF (278/444 Pages) Texas Instruments – Multimedia Device

OMAP4460
Public Version
SWPS046A – JANUARY 2012
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Table 5-58. McBSP3 Switching Characteristics—I2S/PCM—Master Mode⁽⁴⁾⁽⁸⁾ (continued)
NO.
PARAMETER
OPP100, OPP119
OPP50
UNIT
MIN
MAX
MIN
MAX
For balls: AF25 / AE25 / AF26 (abe_mcbsp3_dx / abe_mcbsp3_clkx / abe_mcbsp3_fsx)—Multiplexing mode 1
BM0
BM1
BM2
BM3
1 / t_c(clk)
t_w(clkL)
t_w(clkH)
t_dc(clk)
t_j(clk)
t_R(clk)
t_F(clk)
t_d(clkAE-fsV)
Frequency⁽¹⁾, output abe_mcbsp3_clk⁽⁵⁾ clock
Typical pulse duration, output abe_mcbsp3_clk⁽⁵⁾ low
Typical pulse duration, output abe_mcbsp3_clk⁽⁵⁾ high
Duty cycle error, output abe_mcbsp3_clk⁽⁵⁾
Jitter standard deviation⁽³⁾, output abe_mcbsp3_clk⁽⁵⁾
Rise time, output abe_mcbsp3_clk⁽⁵⁾
Fall time, output abe_mcbsp3_clk⁽⁵⁾
Delay time, output abe_mcbsp3_clk⁽⁵⁾ active edge to
output abe_mcbsp3_fs⁽⁶⁾ valid
24.576⁽⁷⁾
0.5*P⁽²⁾
0.5*P⁽²⁾
–2035 2035
65
400
6500
400
6500
0.9
11.0
12.288⁽⁷⁾
0.5*P⁽²⁾
0.5*P⁽²⁾
–4069 4069
65
400
6500
400
6500
1.0
22.6
MHz
ns
ns
ps
ps
ps
ps
ns
BM4
t_{d(clkxAE-dxV)}
t_R(fs)
t_F(fs)
t_R(dx)
t_F(dx)
Delay time, output abe_mcbsp3_clkx active edge to
output abe_mcbsp3_dx valid
Rise time, output abe_mcbsp3_fs⁽⁶⁾
Fall time, output abe_mcbsp3_fs⁽⁶⁾
Rise time, output abe_mcbsp3_dx
Fall time, output abe_mcbsp3_dx
0.9
11.0
1.0
22.6
ns
400
6500
400
6500
ps
400
6500
400
6500
ps
400
6500
400
6500
ps
400
6500
400
6500
ps
(1) Related to the output abe_mcbsp3_clkx / abe_mcbsp3_clkr maximum and minimum frequency programmable in McBSP module by
setting the configuration register SRGR1_REG[7..0].
For more information regarding the registers configuration see the Serial Communication Interface / Multichannel Buffered Serial Port
(McBSP) / MCBSP Register Manual / MCBSP Registers / MCBSP Register Summary Table section of the OMAP4460 TRM.
(2) P = abe_mcbsp3_clkx / abe_mcbsp3_clkr output clk period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
(4) The timings apply to all configurations regardless of abe_mcbsp3_clk polarity and which clock edges are used to drive output data and
capture input data.
(5) abe_mcbsp3_clk corresponds to either abe_mcbsp3_clkx or abe_mcbsp3_clkr; abe_mcbsp3_clkr is available in 6-pin mode only.
(6) abe_mcbsp3_fs corresponds to either abe_mcbsp3_fsx or abe_mcbsp3_fsr; abe_mcbsp3_fsr is available in 6-pin mode only.
(7) This McBSP3 output clock frequency is based on an output ABE DPLL configured at 196.608 MHz.
For more information regarding the registers configuration, see the Power, Reset and Clock Management / Clock Management
Functional Description / Internal Clock Sources/Generators / DPLL_ABE Description section of the OMAP4460 TRM
(8) See DM Operating Condition Addendum for CORE OPP voltages.
5.6.1.2.2 McBSP3—I2S/PCM Full and Half Cycle—Slave Mode—12 MHz
Table 5-59. McBSP3 Timing Requirements—I2S/PCM—Slave Mode^(4)(5)(8)
NO.
PARAMETER
OPP100, OPP119
OPP50
UNIT
MIN
MAX
MIN
MAX
For balls: AH17 / AE16 / AF16 / AG16 (abe_mcbsp3_dr / abe_mcbsp3_dx / abe_mcbsp3_clkx / abe_mcbsp3_fsx)—Multiplexing
mode 2
BS0
BS1
BS2
BS3
1 / t_c(clk)
t_w(clkL)
t_w(clkH)
t_dc(clk)
t_j(clk)
t_{su(fsV-clkAE)}
Frequency⁽¹⁾, abe_mcbsp3_clk⁽⁶⁾
Typical pulse duration, abe_mcbsp3_clk⁽⁶⁾ low
Typical pulse duration, abe_mcbsp3_clk⁽⁶⁾ high
Duty cycle error, abe_mcbsp3_clk⁽⁶⁾
Cycle jitter⁽³⁾, abe_mcbsp3_clk⁽⁶⁾
Setup time, abe_mcbsp3_fs⁽⁷⁾ valid before
abe_mcbsp3_clk⁽⁶⁾ active edge
12.288
0.5*P⁽²⁾
0.5*P⁽²⁾
–2035 2035
1221
14.8
6.144
0.5*P⁽²⁾
0.5*P⁽²⁾
–4069 4069
2000
30.8
MHz
ns
ns
ps
ps
ns
BS4
t_h(clkAE-fsV)
Hold time, abe_mcbsp3_fs⁽⁷⁾ valid after
14.8
30.8
ns
abe_mcbsp3_clk⁽⁶⁾ active edge
BS6
t_{su(drV-clkAE)}
Setup time, abe_mcbsp3_dr valid before
14.8
30.8
ns
abe_mcbsp3_clk⁽⁶⁾ active edge
BS7
t_h(clkAE-drV)
Hold time, abe_mcbsp3_dr valid after
abe_mcbsp3_clk⁽⁶⁾ active edge
14.8
30.8
ns
278 Timing Requirements and Switching Characteristics
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