OMAPL137-HT Datasheet, PDF (351/444 Pages) Texas Instruments – Multimedia Device

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OMAP4460
www.ti.com
SWPS046A – JANUARY 2012
i2cX_sda
i2cX_scl
START
START REPEAT
START
STOP
I5
I8
I6
I1 I2
I3
I4
I6
I7
Figure 5-101. I²C and SmartReflex—Standard and Fast Modes⁽¹⁾
SWPS040-061
(1) In i2cX, X is equal to 1, 2, 3 or 4, or sr for SmartReflex.
5.6.9.2 I²C and SmartReflex—High-Speed Mode
PCB conditions:
NOTE
• Far End Load is less than 30 pF: for more information regarding LB1, LB0 Far End Load
IO settings, see Control Module / Control Module Functional Description/ Functional
Register Description / I2Cx I/Os Group Pullupresx Controls and Load Range Settings
section of OMAP4460 TRM.
• Maximum trace length is less than 20 cm.
• Characteristic impedance is between 20 Ω to 70 Ω.
Table 5-177. I²C and SmartReflex—High-Speed Mode⁽⁶⁾
NO.
IH1
IH2
IH3
IH4
IH5
IH6
IH7
f_scl
t_w(sclH)
t_w(sclL)
t_{su(sdaV-sclH)}
t_{h(sclH–sdaV)}
t_{su(sclH–sdaL)}
t_{h(sdaL–sclH)}
t_{su(sclH–sdaH)}
t_R(scl)
t_R(scl)
t_F(scl)
t_R(sda)
t_F(sda)
C_B
PARAMETER
Frequency, clock i2cx_scl⁽³⁾
Pulse duration, clock i2cx_scl⁽³⁾ high
Pulse duration, clock i2cx_scl⁽³⁾ low
Setup time, data i2cx_sda⁽³⁾ valid before clock i2cx_scl⁽³⁾ active
level
Hold time, data i2cx_sda⁽³⁾ valid after clock i2cx_scl⁽³⁾ active
level
Setup time, clock i2cx_scl⁽³⁾ high before data i2cx_sda⁽³⁾ low (for
a START⁽²⁾ condition or a repeated START condition)
Hold time, clock i2cx_scl⁽³⁾ high after data i2cx_sda⁽³⁾ low (for a
START⁽²⁾ condition or a repeated START condition)
Setup time, clock i2cx_scl⁽³⁾ high before data i2cx_sda⁽³⁾ high
(for a STOP condition)
Rise time, clock i2cx_scl⁽³⁾
Rise time, clock i2cx_scl⁽³⁾ after a repeated START condition
and after a bit acknowledge
Fall time, clock i2cx_scl⁽³⁾
Rise time, data i2cx_sda⁽³⁾
Fall time, data i2cx_sda⁽³⁾
Capacitive load for each bus line
MIN
60⁽¹⁾
160⁽¹⁾
10
0⁽⁴⁾
160
160
160
10
10
10
10
10
MAX
3.4⁽⁵⁾
70
40
80
40
80
80
100
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
(1) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. t_w(sclL) > 2 * t_w(sclH).
(2) After this time, the first clock is generated.
(3) In i2cx, x is equal to 1, 2, 3, or 4 or sr for SmartReflex. Note that sr (SmartReflex) is master transmitter only.
(4) The device provides (via the I²C bus) a minimum hold time (= I2C_FCLK period x 4) for the i2cx_sda⁽³⁾ signal (refer to the fall and rise
times of i2cx_scl⁽³⁾) to bridge the undefined region of the falling edge of i2cx_scl⁽³⁾.
For more information, see the Serial Communication Interface / Multimaster High-Speed I²C Controller / HS I²C Functional Description /
HS I²C Clocks section of the OMAP4460 TRM.
(5) The maximum I2C5 (or SmartReflex) clock frequency in high-speed mode is equal to the SYS_CLK clock frequency (38.4 MHz
maximum) divided by 18, with LB[1:0] = 01 setting on sr_scl (ball AG9, load range = 12 pF to 25 pF and internal pullup resistance = 920
Copyright © 2012, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 351
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