OMAPL137-HT Datasheet, PDF (335/444 Pages) Texas Instruments – Multimedia Device

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OMAP4460
www.ti.com
SWPS046A – JANUARY 2012
Table 5-147. High-Speed USBB1 Timing Conditions—ULPI TLL Mode—Master Mode—1.8 V^(1)(2)(3)
SYSTEM CONDITION PARAMETER
VALUE
UNIT
MIN
MAX
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
PCB Conditions
1.00
3.00
ns
1.00
3.00
ns
Number of external peripherals
1
Far end load
5
pF
Trace length
5
cm
Characteristics impedance
30
60
Ω
(1) IO settings:
– usbb1_ulpitll_clk (ball AE18): DS0 = 0
For more information, see Control Module / Control Module Functional Description/ Functional Register Description / Signal Integrity
Parameter Control Registers with Pad Group Assignment / I/O cells with Configurable Output Driver Impedance section of the
OMAP4460 TRM.
– usbb1_ulpitll_stp (ball AG19): MB[1:0] = 11 and LB0 = 1
– usbb1_ulpitll_dir (ball AF19): MB[1:0] = 11 and LB0 = 1
– usbb1_ulpitll_nxt (ball AE19): MB[1:0] = 11 and LB0 = 1
– usbb1_ulpitll_dat[7:0] (balls AG16 / AF16 / AE16 / AH17 / AF17 / AE17 / AG18 / AF18): MB[1:0] = 11 and LB0 = 1
For more information, see Control Module / Control Module Functional Description/ Functional Register Description / Signal Integrity
Parameter Control Registers with Pad Group Assignment / Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings
section of the OMAP4460 TRM.
– Corresponding voltage: 1.8 V
(2) In this table the rise and fall times are calculated for 10% to 90% of VDDS. For more information on the corresponding OMAP4 VDDS
power supply name, see Table 2-1, POWER [9] column with the ball name.
(3) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm typical x trace length (cm).
Table 5-148. High-Speed USBB1 Timing Requirements—ULPI TLL Mode—Master Mode—1.8 V⁽¹⁾
NO.
PARAMETER
OPP100, OPP119
MIN
MAX
For ball: AE18 (usbb1_ulpitll_clk)
UT4
t_{su(ctrlV-clkH)}
Setup time, usbb1_ulpitll_stp valid before
usbb1_ulpitll_clk rising edge
5.78
UT5
t_{h(clkH-ctrlV)}
Hold time, usbb1_ulpitll_stp valid after
usbb1_ulpitll_clk rising edge
0.09
UT6
t_su(dV-clkH)
Setup time, usbb1_ulpitll_dat[7:0] valid before
5.78
usbb1_ulpitll_clk rising edge
UT7
t_h(clkH-dV)
Hold time, usbb1_ulpitll_dat[7:0] valid after
usbb1_ulpitll_clk rising edge
0.09
For balls: AG19 / AF19 / AE19 / AF18 / AG18 / AE17 / AF17 / AH17 / AE16 / AF16 / AG16
(usbb1_ulpitll_stp, usbb1_ulpitll_dir, usbb1_ulpitll_nxt, usbb1_ulpitll_dat[7:0])
UT4
t_{su(ctrlV-clkH)}
Setup time, usbb1_ulpitll_stp valid before
usbb1_ulpitll_clk rising edge
5.86
UT5
t_{h(clkH-ctrlV)}
Hold time, usbb1_ulpitll_stp valid after
usbb1_ulpitll_clk rising edge
0.13
UT6
t_su(dV-clkH)
Setup time, usbb1_ulpitll_dat[7:0] valid before
5.86
usbb1_ulpitll_clk rising edge
UT7
t_h(clkH-dV)
Hold time, usbb1_ulpitll_dat[7:0] valid after
usbb1_ulpitll_clk rising edge
0.13
OPP50
MIN
MAX
5.78
0.09
5.78
0.09
5.86
0.13
5.86
0.13
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Copyright © 2012, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 335
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