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OMAPL137-HT Datasheet, PDF (231/444 Pages) Texas Instruments – Multimedia Device
Public Version
OMAP4460
www.ti.com
SWPS046A – JANUARY 2012
Table 5-18. EMIF Switching Characteristics—DDR Mode(5)(6) (continued)
NO.
PARAMETER
DD407
DD408
td(DQSOV-
DQSOHZ)
tw(DQO/DM)
Delay time, lpddr2_dqsX(1) last edge to
lpddr2_dqsX(1) high impedance state
Pulse duralion, lpddr2_dqY(2) and
lpddr2_dmX(1) high/low duration
SDRAM Core Parameters
DD500
tc(ACT-ACT)s Cycle time, ACTIVE to ACTIVE
command
DD501
tw(SRL)s
Pulse duralion, lpddr2_cke during SELF
REFRESH low duration
DD502
tc(SR-VAL)s
Cycle time, SELF REFRESH to VALID
command
DD503
DD504
td(DPWDN)s
td(PWDN)s
Delay time, POWER DOWN exit time
Delay time, DEEP POWER DOWN
command
DD505
DD506
tc(RD-RD)s
tc(RD-PRE)s
Cycle time, READ to READ command
Cycle time, READ to PRECHARGE
command
DD507
DD508
tc(ACT-RD)s
td(PRE)s
Cycle time, ACTIVE to READ command
Delay time, PRECHARGE command
(8-bank)
DD509
tc(ACT-PRE)s Cycle time, ACTIVE to PRECHARGE
command
DD510
DD511
DD512
DD513
DD514
td(WRREC)s
tc(WR-RD)s
tc(ACTBA-
ACTBB)s
tc(ACT-4B-
ACT)s
tc(REF)s
Delay time, WRITE recovery time
Cycle time, WRITE to READ command
Cycle time, ACTIVE bank A to ACTIVE
bank B command
Cycle time, Four banks ACTIVE to
ACTIVE command
Cycle time, Four banks REFRESH
Command
NVM Core Parameters
DD601
DD602
DD603
tc(ACT-
RD/WR)n
tc(ACTBA-
ACTBB)n
tc(ACT-ACT)n
Cycle time, ACTIVE to READ or WRITE
command
Cycle time, ACTIVE bank A to ACTIVE
bank B command
Cycle time, ACTIVE to ACTIVE
command
DD604
DD605
DD606
DD607
tc(CAS-CAS)n
tc(WRREC-
ACT)n
tc(WR-RD)n
tc(PRE-ACT)n
Cycle time, CAS to CAS command
Cycle time, WRITE recovery Time
before ACTIVE
Cycle time, WRITE to READ command
Cycle time, PRECHARGE to ACTIVE
command
DD608
tc(ACT-PRE)n Cycle time, ACTIVE to PREACTIVE
command
DD609
tc(EXPWDN-
VAL)n
Cycle time, EXIT POWER DOWN to
next Valid command
Mode Register Parameters
DD700
td(MRW)
Delay time, MODE REGISTER WRITE
command
DD701
td(MRR)
Delay time, MODE REGISTER READ
command
ZQ Calibration Parameters
OPP100, OPP119
MIN
MAX
0.4
0.5
DD508 +
DD509
15
DD514 + 10
7.5
500
2
7.5
18
18
42
15
7.5
10
50
A(4)
70000
15
255
DD601
DD601
2
15
7.5
3
DD601
10
5
2
OPP50
MIN
MAX
0.4
0.5
DD508 +
DD509
15
DD514 + 10
10
500
2
10
18
18
42
15
10
10
50
A(4)
70000
25
255
DD601
DD601
2
15
10
3
DD601
20
5
2
UNIT
DD100
DD100
ns
ns
ns
ns
µs
DD100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DD100
ns
ns
DD100
ns
ns
DD100
DD100
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Timing Requirements and Switching Characteristics 231
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