OMAPL137-HT Datasheet, PDF (333/444 Pages) Texas Instruments – Multimedia Device

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OMAP4460
SWPS046A – JANUARY 2012
usbb1_mm_txen
usbb1_mm_txdat
FSU19
Transmit
FSU22
Receive
FSU17
FSU18
usbb1_mm_txse0
FSU20
FSU21
FSU23
FSU17
FSU18
SWPS040-135
Figure 5-89. Low- / Full-Speed USBB1—Bidirectional TLL 3-pin Mode—1.8 V
5.6.8.3.5 High-Speed USBB1 (HSUSB)—ULPI SDR Mode—Slave Mode
Table 5-145 and Table 5-146 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-90).
Table 5-144. High-Speed USBB1 Timing Conditions—ULPI SDR Mode—1.8 V^(1)(2)(3)
SYSTEM CONDITION PARAMETER
VALUE
UNIT
MIN
MAX
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
PCB Conditions
1.00
3.00
ns
1.00
3.00
ns
Number of external peripherals
1
Far end load
5
pF
Trace length
5
cm
Characteristics impedance
30
60
Ω
(1) IO settings:
– usbb1_ulpiphy_clk (ball AE18): DS0 = 0
For more information, see Control Module / Control Module Functional Description/ Functional Register Description / Signal Integrity
Parameter Control Registers with Pad Group Assignment / I/O cells with Configurable Output Driver Impedance section of the
OMAP4460 TRM.
– usbb1_ulpiphy_stp (ball AG19): MB[1:0] = 11 and LB0 = 1
– usbb1_ulpiphy_dir (ball AF19): MB[1:0] = 11 and LB0 = 1
– usbb1_ulpiphy_nxt (ball AE19): MB[1:0] = 11 and LB0 = 1
– usbb1_ulpiphy_dat[7:0] (balls AG16 / AF16 / AE16 / AH17 / AF17 / AE17 / AG18 / AF18): MB[1:0] = 11 and LB0 = 1
For more information, see Control Module / Control Module Functional Description/ Functional Register Description / Signal Integrity
Parameter Control Registers with Pad Group Assignment / Low Speed I/Os Combined Slew Rate vs TL Length and Load Settings
section of the OMAP4460 TRM.
– Corresponding voltage: 1.8 V
(2) In this table the rise and fall times are calculated for 10% to 90% of VDDS. For more information on the corresponding OMAP4 VDDS
power supply name, see Table 2-1, POWER [9] column with the ball name.
(3) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm typical x trace length (cm).
Table 5-145. High-Speed USBB1 Timing Requirements—ULPI SDR Mode—Slave Mode—1.8 V⁽⁴⁾
NO.
US1
US2
US3
US5
1 / t_c(clk)
t_w(clkH)
t_w(clkL)
t_dc(clk)
t_j(clk)
t_{su(ctrlV-clkH)}
PARAMETER
Frequency⁽¹⁾, usbb1_ulpiphy_clk
Typical pulse duration, usbb1_ulpiphy_clk high
Typical pulse duration, usbb1_ulpiphy_clk low
Duty cycle error, usbb1_ulpiphy_clk
Jitter standard deviation⁽³⁾, usbb1_ulpiphy_clk
Setup time, usbb1_ulpiphy_dir and usbb1_ulpiphy_nxt valid before
usbb1_ulpiphy_clk rising edge
OPP100, OPP119
MIN
MAX
60
0.5*P⁽²⁾
0.5*P⁽²⁾
–833
833
500
6.73
UNIT
MHz
ns
ns
ps
ps
ns
Copyright © 2012, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 333
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