TMS320DM8127_14 Datasheet, PDF (344/365 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
SPI_SCS[x] (Out)
PHA=0
EPOL=1
8
SPI_SCLK (Out) ^POL=0
SPI_SCLK (Out)
POL=1
SPI_D[x] (In)
4
5
Bit n-1
4
5
Bit n-2
1
3
2
1
2
3
Bit n-3
Bit n-4
Bit 0
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9
SPI_SCS[x] (Out)
PHA=1
EPOL=1
SPI_SCLK (Out) ^POL=0
SPI_SCLK (Out)
POL=1
SPI_D[x] (In)
1
3
8
2
1
2
3
4
5
Bit n-1
4
5
Bit n-2
Bit n-3
Bit 1
Figure 9-90. SPI Master Mode Receive Timing
9
Bit 0
Table 9-101. Timing Requirements for SPI - Slave Mode
(see Figure 9-91 and Figure 9-92)
NO.
1 t_c(SPICLK)
2 t_w(SPICLKL)
3 t_w(SPICLKH)
4 t_{su(MOSI-SPICLK)}
5 t_{h(SPICLK-MOSI)}
6 t_{d(SPICLK-MISO)}
7 t_d(SCS-MISO)
8 t_{su(SCS-SPICLK)}
Cycle time, SPI_CLK⁽¹⁾⁽²⁾
Pulse duration, SPI_CLK low⁽¹⁾
Pulse duration, SPI_CLK high⁽¹⁾
Setup time, SPI_D[x] valid before SPI_CLK active edge ⁽¹⁾
Hold time, SPI_D[x] valid after SPI_CLK active edge ⁽¹⁾
Delay time, SPI_CLK active edge to SPI_D[x] transition⁽¹⁾
Delay time, SPI_SCS[x] active edge to SPI_D[x]
transition ⁽⁵⁾
Setup time, SPI_SCS[x] valid before SPI_CLK first edge⁽¹⁾
OPP100/120/166
MIN
62.5 ⁽³⁾
0.5*P - 3⁽⁴⁾
0.5*P - 3⁽⁴⁾
MAX
12.92
12.92
-4.00
17.1
17.1
12.92
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the input maximum frequency supported by the SPI module.
(3) Maximum frequency = 16 MHz
(4) P = SPICLK period.
(5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
344 Peripheral Information and Timings
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