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TMS320DM8127_14 Datasheet, PDF (1/365 Pages) Texas Instruments – DaVinci Video Processors | |||
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TMS320DM8127
SPRS712C â JUNE 2012 â REVISED MARCH 2014
TMS320DM8127 DaVinci⢠Video Processors
Check for Samples: TMS320DM8127
1 High-Performance System-on-Chip (SoC)
1.1 Features
1
⢠High-Performance DaVinci Video Processors
â Up to 1-GHz ARM® Cortex®-A8 RISC Core
â Up to 750-MHz C674x VLIW DSP
â Up to 6000 MIPS and 4500 MFLOPS
â Fully Software-Compatible with C67x+, C64x+
⢠ARM Cortex-A8 Core
â ARMv7 Architecture
⢠In-Order, Dual-Issue, Superscalar Processor
Core
⢠Neon⢠Multimedia Architecture
⢠Supports Integer and Floating Point
⢠Jazelle® RCT Execution Environment
⢠ARM Cortex-A8 Memory Architecture
â 32KB of Instruction and Data Caches
â 256KB of L2 Cache
â 64KB of RAM, 48KB of Boot ROM
⢠TMS320C674x Floating-Point VLIW DSP
â 64 General-Purpose Registers (32-Bit)
â Six ALU (32-/40-Bit) Functional Units
⢠Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
⢠Supports up to Four SP Adds Per Clock and
Four DP Adds Every Two Clocks
⢠Supports up to Two Floating-Point (SP or
DP) Approximate Reciprocal or Square Root
Operations Per Cycle
â Two Multiply Functional Units
⢠Mixed-Precision IEEE Floating-Point Multiply
Supported up to:
â 2 SP x SP â SP Per Clock
â 2 SP x SP â DP Every Two Clocks
â 2 SP x DP â DP Every Three Clocks
â 2 DP x DP â DP Every Four Clocks
⢠Fixed-Point Multiply Supports Two 32 x 32
Multiplies, Four 16 x 16-Bit Multiplies
Including Complex Multiplies, or Eight 8 x 8-
Bit Multiplies per Clock Cycle
⢠128KB of On-Chip Memory Controller (OCMC)
RAM
⢠Imaging Subsystem (ISS)
â Camera Sensor Connection
⢠Parallel Connection for Raw (up to 16-Bit)
and BT.656 or BT.1120 (8- and 16-Bit)
⢠CSI2 Serial Connection
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â Image Sensor Interface (ISIF) for Handling
Image and Video Data From the Camera
Sensor
â Image Pipe Interface (IPIPEIF) for Image and
Video Data Connection Between Camera
Sensor, ISIF, IPIPE, and DRAM
â Image Pipe (IPIPE) for Real-Time Image and
Video Processing
â Resizer
⢠Resizing Image and Video From 1/16x to 8x
⢠Generating Two Different Resizing Outputs
Concurrently
â Hardware 3A Engine (H3A) for Generating Key
Statistics for 3A (AE, AWB, and AF) Control
⢠Face Detect Engine (FD)
â Hardware Face Detection for up to 35 Faces at
OPP100
⢠Programmable High-Definition Video Image
Coprocessing (HDVICP v2) Engine
â Encode, Decode, Transcode Operations
â H.264, MPEG-2, VC-1, MPEG-4, SP/ASP,
JPEG/MJPEG
⢠Media Controller
â Controls the HDVPSS and ISS
⢠Endianness
â ARM and DSP Instructions/Data â Little Endian
⢠HD Video Processing Subsystem (HDVPSS)
â One 165-MHz HD Video Capture Input
⢠One 16- or 24-Bit Input, Splittable into Dual
8-Bit SD Capture Ports
â Two 165-MHz HD Video Display Outputs
⢠One 16-, 24-, or 30-Bit Output and One 16-
or 24-Bit Output
â Composite or S-Video Analog Output
â Macrovision® Support Available
â Digital HDMI 1.3 Transmitter With Integrated
PHY
â Advanced Video Processing Features Such as
Scan, Format, Rate Conversion
â Three Graphics Layers and Compositors
⢠Dual 32-Bit DDR2/DDR3 SDRAM Interfaces
â Supports up to DDR2-800 and DDR3-1066
â Up to Eight x 8 Devices Total 2GB of Total
Address Space
â Dynamic Memory Manager (DMM)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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