TMS320DM8127_14 Datasheet, PDF (228/365 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
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9.6 Ethernet MAC Switch (EMAC SW)
The EMAC SW controls the flow of packet data between the device and two external Ethernet PHYs, with
hardware flow control and quality-of-service (QOS) support. The EMAC SW contains a 3-port gigabit
switch, where one port is internally connected and the other two ports are brought out externally. Each of
the external EMAC ports supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX (100 Mbps), in
either half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode.
The EMAC SW controls the flow of packet data from the device to the external PHYs. The EMAC0/1 ports
on the device support four interface modes: Media Independent Interface (MII), Gigabit Media
Independent Interface (GMII), Reduced Media Independent Interface (RMII) and Reduced Gigabit Media
Independent Interface (RGMII). In addition, a single MDIO interface is pinned out to control the PHY
configuration and status monitoring. Multiple external PHYs can be controlled by the MDIO interface.
The EMAC SW module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
Deviating from this standard, the EMAC SW module does not use the Transmit Coding Error signal
MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the
EMAC SW will intentionally generate an incorrect checksum by inverting the frame CRC, so that the
transmitted frame will be detected as an error by the network. In addition, the EMAC SW I/Os operate at
3.3 V and are not compatible with 2.5-V I/O signaling. Therefore, only Ethernet PHYs with 3.3-V I/O
interface should be used.
In networking systems, packet transmission and reception are critical tasks. The communications port
programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software
and communications modules. The CPPI block contains 2048 words of 32-bit buffer descriptor memory
that holds up to 512 buffer descriptors.
For more detailed information on the EMAC SW module, see the 3PSW Ethernet Subsystem chapter of
the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).
9.6.1 EMAC Peripheral Register Descriptions
ARM/L3 MASTERS
EMAC HEX
ADDRESS RANGE
0x4A10 0000
0x4A10 0004
0x4A10 0008
0x4A10 000C
0x4A10 0010
0x4A10 0014
0x4A10 0018
0x4A10 001C
0x4A10 0020
0x4A10 0024
0x4A10 0028
0x4A10 002C
0x4A10 0030
0x4A10 0034
0x4A10 0038
Table 9-14. Ethernet MAC Switch Registers
ACRONYM
REGISTER NAME
CPSW_ID_VER
CPSW_CONTROL
CPSW_SOFT_RESET
CPSW_STAT_PORT_EN
CPSW_PTYPE
CPSW_SOFT_IDLE
CPSW_THRU_RATE
CPSW_GAP_THRESH
CPSW_TX_START_WDS
CPSW_FLOW_CONTROL
P0_MAX_BLKS
P0_BLK_CNT
P0_TX_IN_CTL
P0_PORT_VLAN
P0_TX_PRI_MAP
CPSW ID Version Register
CPSW Switch Control Register
CPSW Soft Reset Register
CPSW Statistics Port Enable Register
CPSW Transmit Priority Type Register
CPSW Software Idle
CPSW Throughput Rate
CPSW CPGMAC_SL Short Gap Threshold
CPSW Transmit Start Words
CPSW Flow Control
CPSW Port 0 Maximum FIFO Blocks Register
CPSW Port 0 FIFO Block Usage Count Register (Read Only)
CPSW Port 0 Transmit FIFO Control
CPSW Port 0 VLAN Register
CPSW Port 0 Tx Header Priority to Switch Priority Mapping Register
228 Peripheral Information and Timings
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