TMS320DM8127_14 Datasheet, PDF (312/365 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
www.ti.com
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Figure 9-73. ADDR_CTRL Routing for One DDR3 Device
9.13.4.2.4.12 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point-to-point, so its
definition is simple.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure
there are nearby ground vias to allow the return currents to transition between reference planes if both
reference planes are ground or DVDD_DDR. Ensure there are nearby bypass capacitors to allow the
return currents to transition between reference planes if one of the reference planes is ground. The goal is
to minimize the size of the return current loops.
9.13.4.2.4.12.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 9-74
and Figure 9-75 show these topologies.
Processor
DQS
IO Buffer
DQSn+
DQSn-
Routed Differentially
n = 0, 1, 2, 3
Figure 9-74. DQS Topology
DDR
DQS
IO Buffer
Processor
DDR
DQ and DM
Dn
DQ and DM
IO Buffer
IO Buffer
n = 0, 1, 2, 3
Figure 9-75. DQ/DM Topology
9.13.4.2.4.12.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
Figure 9-76 and Figure 9-77 show the DQS and DQ/DM routing.
312 Peripheral Information and Timings
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