TMS320DM8127_14 Datasheet, PDF (272/365 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
www.ti.com
9.11 Inter-Integrated Circuit (I2C)
The device includes four inter-integrated circuit (I2C) modules which provide an interface to other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through
the I2C module. The I2C port does not support CBUS compatible devices.
The I2C port supports the following features:
• Compatible with Philips I2C Specification Revision 2.1 (January 2000)
• Standard and fast modes from 10 - 400 Kbps (no fail-safe I/O buffers)
• Noise filter to remove noise 50 ns or less
• Seven- and ten-bit device addressing modes
• Multimaster transmitter/slave receiver mode
• Multimaster receiver/slave transmitter mode
• Combined master transmit/receive and receive/transmit modes
• Two DMA channels, one interrupt line
• Built-in FIFO (32 byte) for buffered read or write.
For more detailed information on the I2C peripheral, see the Inter-Integrated Circuit (I2C) Controller
Module chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual
(Literature Number: SPRUGZ8).
9.11.1 I2C Peripheral Register Descriptions
I2C0
0x4802 8000
0x4802 8004
0x4802 8010
0x4802 8020
0x4802 8024
0x4802 8028
0x4802 802C
0x4802 8030
0x4802 8034
0x4802 8038
0x4802 803C
0x4802 8040
0x4802 8044
0x4802 8048
0x4802 804C
0x4802 8090
0x4802 8094
0x4802 8098
0x4802 809C
0x4802 80A4
0x4802 80A8
Table 9-45. I2C Registers
HEX ADDRESS
I2C1
I2C2
0x4802 A000
0x4819 C000
0x4802 A004
0x4819 C004
0x4802 A010
0x4819 C010
0x4802 A020
0x4819 C020
0x4802 A024
0x4819 C024
0x4802 A028
0x4802 A02C
0x4802 A030
0x4802 A034
0x4802 A038
0x4819 C028
0x4819 C02C
0x4819 C030
0x4819 C034
0x4819 C038
0x4802 A03C
0x4819 C03C
0x4802 A040
0x4819 C040
0x4802 A044
0x4819 C044
0x4802 A048
0x4802 A04C
0x4802 A090
0x4802 A094
0x4802 A098
0x4802 A09C
0x4802 A0A4
0x4802 A0A8
0x4819 C048
0x4819 C04C
0x4819 C090
0x4819 C094
0x4819 C098
0x4819 C09C
0x4819 C0A4
0x4819 C0A8
I2C3
0x4819 E000
0x4819 E004
0x4819 E010
0x4819 E020
0x4819 E024
0x4819 E028
0x4819 E02C
0x4819 E030
0x4819 E034
0x4819 E038
0x4819 E03C
0x4819 E040
0x4819 E044
0x4819 E048
0x4819 E04C
0x4819 E090
0x4819 E094
0x4819 E098
0x4819 E09C
0x4819 E0A4
0x4819 E0A8
ACRONYM
REGISTER NAME
I2C_REVNB_LO Module Revision (LOW BYTES)
I2C_REVNB_HI
Module Revision (HIGH BYTES)
I2C_SYSC
System configuration
I2C_EOI
I2C End of Interrupt
I2C_IRQSTATUS_RA I2C Status Raw
W
I2C_IRQSTATUS I2C Status
I2C_IRQENABLE_SET I2C Interrupt Enable Set
I2C_IRQENABLE_CLR I2C Interrupt Enable Clear
I2C_WE
I2C Wakeup Enable
I2C_DMARXENABLE_ Receive DMA Enable Set
SET
I2C_DMATXENABLE_ Transmit DMA Enable Set
SET
I2C_DMARXENABLE_ Receive DMA Enable Clear
CLR
I2C_DMATXENABLE_ Transmit DMA Enable Clear
CLR
I2C_DMARXWAKE_EN Receive DMA Wakeup
I2C_DMATXWAKE_EN Transmit DMA Wakeup
I2C_SYSS
System Status
I2C_BUF
Buffer Configuration
I2C_CNT
Data Counter
I2C_DATA
Data Access
I2C_CON
I2C Configuration
I2C_OA
I2C Own Address
272 Peripheral Information and Timings
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