TMS320DM8127_14 Datasheet, PDF (217/365 Pages) Texas Instruments – DaVinci Video Processors

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TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
9.4 EDMA
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the device. These data transfers include cache servicing, non-cacheable memory accesses, user-
programmed data transfers, and host accesses.
9.4.1 EDMA Channel Synchronization Events
The EDMA Channel controller supports up to 64 channels that service peripherals and memory. Each
EDMA channel is mapped to a defaul EDMA synchronization event as shown in Table 9-3. By default,
each event uses the parameter entry that matches its event number. However, because the device
includes a channel mapping feature, each event may be mapped to any of 512 parameter table entries.
For more detailed information, see the Enhanced Direct Memory Access Controller chapter of the
TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).
EVENT
NUMBER
2
3
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
36
37
38
39
40
41
42
Table 9-3. EDMA Default Synchronization Events
DEFAULT
EVENT NAME
SDTXEVT1
SDRXEVT1
AXEVT0
AREVT0
AXEVT1
AREVT1
AXEVT2
AREVT2
BXEVT
BREVT
SPI0XEVT0
SPI0REVT0
SPI0XEVT1
SPI0REVT1
SPI0XEVT2
SPI0REVT2
SPI0XEVT3
SPI0REVT3
SDTXEVT0
SDRXEVT0
UTXEVT0
URXEVT0
UTXEVT1
URXEVT1
UTXEVT2
URXEVT2
ISS_DMA_REQ1
ISS_DMA_REQ2
ISS_DMA_REQ3
ISS_DMA_REQ4
CAN_IF1DMA
CAN_IF2DMA
SPI1XEVT0
DEFAULT EVENT DESCRIPTION
SD1 Transmit
SD1 Receive
McASP0 Transmit
McASP0 Receive
McASP1 Transmit
McASP1 Receive
McASP2 Transmit
McASP2 Receive
McBSP Transmit
McBSP Receive
SPI0 Transmit 0
SPI0 Receive 0
SPI0 Transmit 1
SPI0 Receive 1
SPI0 Transmit 2
SPI0 Receive 2
SPI0 Transmit 3
SPI0 Receive 3
SD0 Transmit
SD0 Receive
UART0 Transmit
UART0 Receive
UART1 Transmit
UART1 Receive
UART2 Transmit
UART2 Receive
ISS Event 1
ISS Event 2
ISS Event 3
ISS Event 4
DCAN0 IF1
DCAN0 IF2
SPI1 Transmit 0
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Peripheral Information and Timings 217