TMS320DM8127_14 Datasheet, PDF (299/365 Pages) Texas Instruments – DaVinci Video Processors

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TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
9.13.4.2.4.1 Compatible JEDEC DDR3 Devices
Table 9-66 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-1600 devices in the x8 or x16 widths.
Table 9-66. Compatible JEDEC DDR3 Devices (Per Interface)
NO.
PARAMETER
1 JEDEC DDR3 device speed grade⁽¹⁾
MIN
DDR3-800
MAX
DDR3-
1600 ⁽²⁾
UNIT
2 JEDEC DDR3 device bit width
3 JEDEC DDR3 device count⁽³⁾
x8
x16 Bits
2
8 Devices
(1) DDR3 speed grade depends on desired clock rate. Data rate is 2x the clock rate. For DDR3-800, the clock rate is 400 MHz.
(2) DDR3 devices with speed grades up to DDR3-1600 are supported; however, max clock rate will still be limited to 533 MHz as stated in
Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller.
(3) For valid DDR3 device configurations and device counts, see Section 9.13.4.2.4, Figure 9-54, and Figure 9-55.
9.13.4.2.4.2 PCB Stackup
The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 9-67.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI
performance, or to reduce the size of the PCB footprint. A six-layer stackup is shown in Table 9-68.
Complete stackup specifications are provided in Table 9-69.
LAYER
1
2
3
4
Table 9-67. Minimum PCB Stackup
TYPE
Signal
Plane
Plane
Signal
DESCRIPTION
Top routing mostly vertical
Split power plane
Full ground plane
Bottom routing mostly horizontal
LAYER
1
2
3
4
5
6
Table 9-68. Six-Layer PCB Stackup Suggestion
TYPE
Signal
Plane
Plane
Plane
Plane
Signal
DESCRIPTION
Top routing mostly vertical
Ground
Split power plane
Split power plane or Internal routing
Ground
Bottom routing mostly horizontal
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