TMS320DM8127_14 Datasheet, PDF (340/365 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
www.ti.com
9.18 Serial Peripheral Interface (SPI)
The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed
length (4 to 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is
normally used for communication between the device and external peripherals. Typical applications
include an interface-to-external I/O or peripheral expansion via devices such as shift registers, display
drivers, SPI EEPROMs, and Analog-to-Digital Converters (ADCs).
The SPI supports the following features:
• Master/Slave operation
• Four chip selects for interfacing/control to up to four SPI Slave devices and connection to a single
external Master
• 32-bit shift register
• Buffered receive/transmit data register per channel (1 word deep), FIFO size is 64 bytes
• Programmable SPI configuration per channel (clock definition, enable polarity and word width)
• Supports one interrupt request and two DMA requests per channel.
For more detailed information on the SPI, see the Multichannel Serial Port Interface (McSPI) chapter of
the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).
9.18.1 SPI Peripheral Register Descriptions
SPI0
0x4803 0000
0x4803 0004
0x4803 0008 -
0x4803 000C
0x4803 0010
0x4803 0014 -
0x4803 00FF
0x4803 0100
0x4803 0104 -
0x4803 010C
0x4803 0110
0x4803 0114
0x4803 0118
0x4803 011C
0x4803 0120
0x4803 0124
0x4803 0128
0x4803 012C
0x4803 0130
0x4803 0134
0x4803 0138
Table 9-99. SPI Registers
HEX ADDRESS RANGE
SPI1
SPI2
0x481A 0000
0x481A 2000
0x481A 0004
0x481A 2004
0x481A 0008 -
0x481A 000C
0x481A 0010
0x481A 2008 -
0x481A 200C
0x481A 2010
0x481A 0014 -
0x481A 00FF
0x481A 0100
0x481A 0104 -
0x481A 010C
0x481A 0110
0x481A 2014 -
0x481A 20FF
0x481A 2100
0x481A 2104 -
0x481A 210C
0x481A 2110
0x481A 0114
0x481A 2114
0x481A 0118
0x481A 2118
0x481A 011C
0x481A 211C
0x481A 0120
0x481A 2120
0x481A 0124
0x481A 0128
0x481A 2124
0x481A 2128
0x481A 012C
0x481A 0130
0x481A 0134
0x481A 0138
0x481A 212C
0x481A 2130
0x481A 2134
0x481A 2138
SPI3
0x481A 4000
0x481A 4004
0x481A 4008 -
0x481A 400C
0x481A 4010
0x481A 4014 -
0x481A 40FF
0x481A 4100
0x481A 4104 -
0x481A 410C
0x481A 4110
0x481A 4114
0x481A 4118
0x481A 411C
0x481A 4120
0x481A 4124
0x481A 4128
0x481A 412C
0x481A 4130
0x481A 4134
0x481A 4138
ACRONYM
REGISTER NAME
MCSPI_HL_REV
MCSPI_HL_HWIN
FO
-
SPI REVISION
SPI HARDWARE
INFORMATION
RESERVED
MCSPI_HL_SYSC SPI SYSTEM
ONFIG
CONFIGURATION
-
RESERVED
MCSPI_REVISION REVISION
-
RESERVED
MCSPI_SYSCONF SYSTEM CONFIGURATION
IG
MCSPI_SYSSTAT SYSTEM STATUS
US
MCSPI_IRQSTATU INTERRUPT STATUS
S
MCSPI_IRQENABL INTERRUPT ENABLE
E
MCSPI_WAKEUPE WAKEUP ENABLE
NABLE
MCSPI_SYST SYSTEM TEST
MCSPI_MODULCT MODULE CONTROL
RL
MCSPI_CH0CONF CHANNEL 0 CONFIGURATION
MCSPI_CH0STAT CHANNEL 0 STATUS
MCSPI_CH0CTRL CHANNEL 0 CONTROL
MCSPI_TX0 CHANNEL 0 TRANSMITTER
340 Peripheral Information and Timings
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320DM8127