TMS320DM8127_14 Datasheet, PDF (276/365 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8127
SPRS712C – JUNE 2012 – REVISED MARCH 2014
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9.12 Imaging Subsystem (ISS)
The device Imaging Subsystem captures and processes pixel data from external image and video inputs.
The inputs can be connected to the Image Processing block through the Parallel Camera Interface (CAM)
or the Serial Camera Interface (CSI2). The captured pixel data is processed by the Image Signal
Processor (ISP). In addition, a Timing control module provides flash strobe and mechanical shutter
interfaces. The features of each component of the ISS are described below.
• Parallel Camera (CAM) interface features:
– Input format
• Bayer pattern Raw (up to 16bit) or YCbCr 422 (8bit or 16bit) data.
• ITU-R BT.656/1120 standard format
– Generates HD/VD timing signals and field ID to an external timing generator, or can synchronize to
the external timing generator.
– Support for progressive and interlaced sensors (hardware support for up to 2 fields and firmware
supports for higher number of fields, typically 3-, 4-, and 5-field sensors.
• Serial Camera Interface (CSI2) features:
– Support for 1, 2, 3 or 4 Data-lanes at 1Gb/s per lane for up to 3 Data-lane, and 800 Mbps per lane
for 4 Data-lane
– Transfer pixels to the system memory or to the ISP
– Error detection and correction by the protocol engine
– DMA engine integrated with dedicated FIFO
– 1-D and 2-D addressing mode
– Up to 8 contexts to support 8 dedicated configurations
– Ping-Pong mechanism for double buffering
– All primary and secondary MIPI-defined formats are supported (RGB, RAW, YUV,…)
– On-the-fly DPCM decompression
– On-the-fly image cropping and A-Law/DPCM compression
• Image Sensor Interface (ISIF) features:
– Support for up to 32K pixels (image size) in both the horizontal and vertical direction
– Color space conversion for non-Bayer pattern Raw data
– Digital black clamping with Horizontal/Vertical offset drift compensation
– Vertical Line defect correction based on a lookup table
– Color-dependent gain control and black level offset control
– Ability to control output to the DDR2/DDR3 via an external write enable signal
– Down sampling via programmable culling patterns
– A-law/DPCM compression
– Generating 16-, 12- or 8-bit output to memory
276 Peripheral Information and Timings
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