TMS320DM8148_17 Datasheet, PDF (336/377 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
www.ti.com
MCB_CLK
MCB_FS
MCB_DX
1
4
6
2
5
6
MCB_DX7
3
6
MCB_DX6
MCB_DX0
MCB_DR
8
7
MCB_DR7
MCB_DR6
MCB_DR0
A. The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive
output data and capture input data.
B. MCBSP_CLK corresponds to either MCBSP_CLKX or MCBSP_CLKR; MCBSP_FS corresponds to either
MCBSP_FSX
or
MCBSP_FSR.
McBSP in 6-pin mode: DX and DR as data pins; CLKX, CLKR, FSX and FSR as control pins.
McBSP in 4-pin mode: DX and DR as data pins; CLKX and FSX pins as control pins. The CLKX and FSX pins are
internally looped back via software configuration, respectively to the CLKR and FSR internal signals for data receive.
C. The polarity of McBSP frame synchronization is software configurable.
D. The active clock edge selection of MCBSP_CLK (rising or falling) on which MCBSP_DX data is latched and
MCBSP_DR data is sampled is software configurable.
E. Timing diagrams are for data delay set to 1.
F. For further details about the registers used to configure McBSP, see the Multichannel Buffered Serial Port (McBSP)
chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).
Figure 8-84. McBSP Slave Mode Timing
336 Peripheral Information and Timings
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