TMS320DM8148_17 Datasheet, PDF (276/377 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
www.ti.com
Table 8-43. Switching Characteristics Over Recommended Operating Conditions for HDVPSS Output
(see Figure 8-38 and Figure 8-40)
NO.
1 t_c(CLK)
2 t_w(CLKH)
3 t_w(CLKL)
7 t_t(CLK)
t_d(CLK-AVID)
t_d(CLK-FLD)
t_d(CLK-VSYNC)
t_d(CLK-HSYNC)
6 t_d(CLK-RCR)
t_d(CLK-GYYC)
t_d(CLK-BCBC)
t_d(CLK-YYC)
t_d(CLK-C)
PARAMETER
Cycle time, VOUT[x]_CLK
Pulse duration, VOUT[x]_CLK high (45% of t_c)
Pulse duration, VOUT[x]_CLK low (45% of t_c)
Transition time, VOUT[x]_CLK (10%-90%)
Delay time, VOUT[x]_CLK low (falling) to control valid
Delay time, VOUT[0]_CLK low (falling) to data valid
Delay time, VOUT[1]_CLK low (falling) to data valid
OPP100/120/166
MIN
6.06 ⁽¹⁾
MAX
2.73
2.73
2.64
UNIT
ns
ns
ns
ns
-1.2
2 ns
-1.2
2 ns
(1) For maximum frequency of 165 MHz.
2
VIN[x]A_CLK/
VIN[x]B_CLK/
VOUT[x]_CLK
1
1
3
7
7
Figure 8-38. HDVPSS Clock Timing
276 Peripheral Information and Timings
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