TMS320DM8148_17 Datasheet, PDF (125/377 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
www.ti.com
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
3.2.20 UART
Table 3-36. UART0 Terminal Functions
SIGNAL
NAME
NO.
TYPE ⁽¹⁾
OTHER ⁽²⁾
(3)
MUXED
DESCRIPTION
UART0
UART0_RXD
AH5
I
IPU
DVDD
–
PINCNTL70
DSIS: PIN
UART0 Receive Data Input. Functions as IrDA receive input
in IrDA modes and CIR receive input in CIR mode.
UART0_TXD
AG5
O
IPU
DVDD
–
PINCNTL71
DSIS: PIN
UART0 Transmit Data Output. Functions as CIR transmit
output in CIR mode.
UART0_RTS/
UART4_TXD/
DCAN1_RX/
SPI[1]_SCS[2]/
SD2_SDCD
AF5
O
IPU
DVDD
UART4, DCAN1,
SPI[1], SD2
PINCNTL73
DSIS: PIN
UART0 Request to Send Output. Indicates module is ready
to receive data. Functions as transmit data output in IrDA
modes.
UART0_CTS/
UART4_RXD/
DCAN1_TX/
SPI[1]_SCS[3]/
SD0_SDCD
AE6
I/O
IPU
DVDD
UART4, DCAN1,
SPI[1], SD0
PINCNTL72
DSIS: 1
UART0 Clear to Send Input. Functions as SD transceiver
control output in IrDA and CIR modes.
UART0_DTR/
UART3_CTS/
UART1_TXD/
GP1[4]
AG2
O
IPU
DVDD
UART3, UART1,
GP1
PINCNTL76
DSIS: PIN
UART0 Data Terminal Ready Output
UART0_DSR/
UART3_TXD/
SPI[0]_SCS[2]/
I2C[2]_SDA/
AG4
I
SD1_SDWP/
GP1[3]
IPU
DVDD
UART3, SPI[0],
I2C[2], SD1, GP1
PINCNTL75
DSIS: 1
UART0 Data Set Ready Input
UART0_DCD/
UART3_RXD/
SPI[0]_SCS[3]/
I2C[2]_SCL/
AH4
I
SD1_POW/
GP1[2]
IPU
DVDD
UART3, SPI[0],
I2C[2], SD1, GP1
PINCNTL74
DSIS: 1
UART0 Data Carrier Detect Input
UART0_RIN/
UART3_RTS/
UART1_RXD/
GP1[5]
AF4
I
IPU
DVDD
UART3, UART1,
GP1
PINCNTL77
DSIS: 1
UART0 Ring Indicator Input
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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