TMS320DM8148_17 Datasheet, PDF (164/377 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
HEX
ADDRESS
REGISTER
NAME
PIN
NO.
0x4814 0960
0x4814 0964
0x4814 0968
0x4814 096C
0x4814 0970
0x4814 0974
0x4814 0978
0x4814 097C
0x4814 0980
0x4814 0984
0x4814 0988
0x4814 098C
0x4814 0990
0x4814 0994
0x4814 0998
0x4814 099C
0x4814 09A0
PINCNTL89
PINCNTL90
PINCNTL91
PINCNTL92
PINCNTL93
PINCNTL94
PINCNTL95
PINCNTL96
PINCNTL97
PINCNTL98
PINCNTL99
PINCNTL100
PINCNTL101
PINCNTL102
PINCNTL103
PINCNTL104
PINCNTL105
U26
Y28
V27
W27
V26
AA28
U25
V25
Y27
AB28
Y26
AA27
U24
U23
V24
Y25
AD27
0x4814 09A4 PINCNTL106 V23
0x4814 09A8 PINCNTL107 AE28
0x4814 09AC PINCNTL108 AC27
0x4814 09B0 PINCNTL109 AD28
0x4814 09B4 PINCNTL110 AC28
0x4814 09B8 PINCNTL111 AB27
0x4814 09BC PINCNTL112 AA26
0x4814 09C0 PINCNTL113 L25
0x4814 09C4 PINCNTL114 N23
0x4814 09C8 PINCNTL115 P22
0x4814 09CC PINCNTL116 R24
0x4814 09D0 PINCNTL117 J28
0x4814 09D4 PINCNTL118 K27
0x4814 09D8 PINCNTL119 M24
0x4814 09DC PINCNTL120 L26
0x4814 09E0 PINCNTL121 M23
0x4814 09E4 PINCNTL122 T28
0x4814 09E8 PINCNTL123 K28
REGISTER
RESET
VALUE
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0005 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0006 0000
0x0004 0000
0x0006 0000
0x0004 0000
0x0006 0000
0x0006 0000
0x0006 0000
0x0006 0000
0x0006 0000
0x0006 0000
0x0006 0000
0x0006 0000
0x0006 0000
0x0006 0000
0x0006 0000
Table 4-13. PINCNTLx Registers MUXMODE Functions (continued)
MUXMODE[7:0] SETTINGS
0x1
0x2
0x4
0x8
0x10
GPMC_D[0]
GPMC_D[1]
GPMC_D[2]
GPMC_D[3]
GPMC_D[4]
GPMC_D[5]
GPMC_D[6]
GPMC_D[7]
GPMC_D[8]
GPMC_D[9]
GPMC_D[10]
GPMC_D[11]
GPMC_D[12]
GPMC_D[13]
GPMC_D[14]
GPMC_D[15]
GPMC_A[16]
GPMC_A[17]
GPMC_A[18]
GPMC_A[19]
GPMC_A[20]^(M0)
GPMC_A[21]^(M0)
GPMC_A[22]^(M0)
GPMC_A[23]^(M0)
SD2_DAT[7]
SD2_DAT[6]
SD2_DAT[5]
SD2_DAT[4]
SD2_DAT[3]
SD2_DAT[2]_SDRW
SD2_DAT[1]_SDIRQ
SD2_DAT[0]
SD2_CLK
GPMC_A[24]^(M0)
GPMC_A[25]^(M0)
GPMC_A[26]^(M0)
GPMC_A[27]^(M0)
GPMC_A[1]^(M1)
GPMC_A[2]^(M1)
GPMC_A[3]^(M1)
GPMC_A[4]^(M1)
SPI[2]_SCS[1]
SPI[2]_D[0]^(M0)
SPI[2]_D[1]^(M0)
SPI[2]_SCLK^(M0)
GPMC_A[20]^(M1)
GPMC_A[21]^(M1)
GPMC_A[22]^(M1)
GPMC_A[23]^(M1)
GPMC_CS[7]
HDMI_CEC^(M0)
HDMI_HPDET^(M0)
GPMC_CS[0]
GPMC_CS[1]
GPMC_A[25]^(M1)
0x20
UART2_RXD^(M3)
UART2_TXD^(M3)
EDMA_EVT0^(M1)
0x40
TIM2_IO^(M2)
TIM3_IO^(M2)
TIM4_IO^(M2)
TIM5_IO^(M2)
TIM6_IO^(M2)
TIM7_IO^(M2)
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0x80
BTMODE[0]
BTMODE[1]
BTMODE[2]
BTMODE[3]
BTMODE[4]
BTMODE[5]
BTMODE[6]
BTMODE[7]
BTMODE[8]
BTMODE[9]
BTMODE[10]
BTMODE[11]
BTMODE[12]
BTMODE[13]
BTMODE[14]
BTMODE[15]
GP2[5]^(M0)
GP2[6]^(M0)
GP1[13]^(M0)
GP1[14]^(M0)
GP1[15]^(M0)
GP1[16]^(M0)
GP1[17]^(M0)
GP1[18]^(M0)
GP1[19]
GP1[20]
GP1[21]
GP1[22]
GP2[5]^(M1)
GP2[6]^(M1)
GP1[13]^(M1)
GP1[14]^(M1)
GP1[15]^(M1)
GP1[23]
GP1[24]
164 Device Configurations
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