TMS320DM8148_17 Datasheet, PDF (30/377 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
2.12.4.2 L4 Slow Peripheral Memory Map
www.ti.com
Table 2-7. L4 Slow Peripheral Memory Map
Cortex-A8 and L3 Masters
START
ADDRESS
(HEX)
END ADDRESS
(HEX)
0x4800_0000
0x4800_07FF
C674x DSP
START
END ADDRESS
ADDRESS (HEX)
(HEX)
0x0800_0000
0x0800_07FF
0x4800_0800
0x4800_0FFF
0x0800_0800
0x0800_0FFF
0x4800_1000
0x4800_13FF
0x0800_1000
0x0800_13FF
0x4800_1400
0x4800_17FF
0x0800_1400
0x0800_17FF
0x4800_1800
0x4800_2000
0x4800_8000
0x4801_0000
0x4801_1000
0x4801_2000
0x4802_0000
0x4802_1000
0x4802_2000
0x4802_3000
0x4802_4000
0x4802_5000
0x4802_6000
0x4802_8000
0x4802_9000
0x4802_A000
0x4802_B000
0x4802_C000
0x4802_E000
0x4802_F000
0x4803_0000
0x4803_1000
0x4803_2000
0x4803_3000
0x4803_4000
0x4803_8000
0x4803_A000
0x4803_B000
0x4803_C000
0x4803_E000
0x4803_F000
0x4804_0000
0x4804_1000
0x4804_2000
0x4804_3000
0x4804_4000
0x4800_1FFF
0x4800_7FFF
0x4800_8FFF
0x4801_0FFF
0x4801_1FFF
0x4801_FFFF
0x4802_0FFF
0x4802_1FFF
0x4802_2FFF
0x4802_3FFF
0x4802_4FFF
0x4802_5FFF
0x4802_7FFF
0x4802_8FFF
0x4802_9FFF
0x4802_AFFF
0x4802_BFFF
0x4802_DFFF
0x4802_EFFF
0x4802_FFFF
0x4803_0FFF
0x4803_1FFF
0x4803_2FFF
0x4803_3FFF
0x4803_7FFF
0x4803_9FFF
0x4803_AFFF
0x4803_BFFF
0x4803_DFFF
0x4803_EFFF
0x4803_FFFF
0x4804_0FFF
0x4804_1FFF
0x4804_2FFF
0x4804_3FFF
0x4804_4FFF
0x0800_1800
0x0800_2000
0x0800_8000
0x0801_0000
0x0801_1000
0x0801_2000
0x0802_0000
0x0802_1000
0x0802_2000
0x0802_3000
0x0802_4000
0x0802_5000
0x0802_6000
0x0802_8000
0x0802_9000
0x0802_A000
0x0802_B000
0x0802_C000
0x0802_E000
0x0802_F000
0x0803_0000
0x0803_1000
0x0803_2000
0x0803_3000
0x0803_4000
0x0803_8000
0x0803_A000
0x0803_B000
0x0803_C000
0x0803_E000
0x0803_F000
0x0804_0000
0x0804_1000
0x0804_2000
0x0804_3000
0x0804_4000
0x0800_1FFF
0x0800_7FFF
0x0800_8FFF
0x0801_0FFF
0x0801_1FFF
0x0801_FFFF
0x0802_0FFF
0x0802_1FFF
0x0802_2FFF
0x0802_3FFF
0x0802_4FFF
0x0802_5FFF
0x0802_7FFF
0x0802_8FFF
0x0802_9FFF
0x0802_AFFF
0x0802_BFFF
0x0802_DFFF
0x0802_EFFF
0x0802_FFFF
0x0803_0FFF
0x0803_1FFF
0x0803_2FFF
0x0803_3FFF
0x0803_7FFF
0x0803_9FFF
0x0803_AFFF
0x0803_BFFF
0x0803_DFFF
0x0803_EFFF
0x0803_FFFF
0x0804_0FFF
0x0804_1FFF
0x0804_2FFF
0x0804_3FFF
0x0804_4FFF
SIZE
2KB
2KB
1KB
1KB
2KB
24KB
32KB
4KB
4KB
56KB
4KB
4KB
4KB
4KB
4KB
4KB
8KB
4KB
4KB
4KB
4KB
8KB
4KB
4KB
4KB
4KB
4KB
4KB
16KB
8KB
4KB
4KB
8KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
DEVICE NAME
L4 Slow Configuration –
Address/Protection (AP)
L4 Slow Configuration – Link Agent
(LA)
L4 Slow Configuration – Initiator Port
(IP0)
L4 Slow Configuration – Initiator Port
(IP1)
Reserved
Reserved
Reserved
System MMU Peripheral Registers
System MMU Support Registers
Reserved
UART0 Peripheral Registers
UART0 Support Registers
UART1 Peripheral Registers
UART1 Support Registers
UART2 Peripheral Registers
UART2 Support Registers
Reserved
I2C0 Peripheral Registers
I2C0 Support Registers
I2C1 Peripheral Registers
I2C1 Support Registers
Reserved
TIMER1 Peripheral Registers
TIMER1 Support Registers
SPI0 Peripheral Registers
SPI0 Support Registers
GPIO0 Peripheral Registers
GPIO0 Support Registers
Reserved
McASP0 CFG Peripheral Registers
McASP0 CFG Support Registers
Reserved
McASP1 CFG Peripheral Registers
McASP1 CFG Support Registers
Reserved
TIMER2 Peripheral Registers
TIMER2 Support Registers
TIMER3 Peripheral Registers
TIMER3 Support Registers
TIMER4 Peripheral Registers
30
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