TMS320DM8148_17 Datasheet, PDF (195/377 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
www.ti.com
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
Table 7-10. Switching Characteristics Over Recommended Operating Conditions During Reset
NO.
9 ^td(PORH-
RSTOUTL)
10 ^td(RSTH-
RSTOUTD)
(see Figure 7-5) (continued)
PARAMETER
Delay time, POR high to RSTOUT_WD_OUT driven based on latched BTMODE[11]
value^{(1) (2)}
Delay time, RESET high to RSTOUT_WD_OUT driven based on latched BTMODE[11]
value^{(1) (2)}
OPP100
UNIT
MIN
MAX
0
2P ns
0
2P ns
Figure 7-4 shows the Power-Up Timing. Figure 7-5 shows the Warm Reset (RESET) Timing. Max Reset
Timing is identical to Warm Reset Timing, except the BTMODE[15:0] pins are not re-latched.
DEV_CLKIN/
AUX_CLKIN^(A)
Power
Supplies
Ramping
POR
Clock Source Stable
1
Power Supplies Stable
RESET
RSTOUT_WD_OUT
BTMODE[15:0]
Other I/O Pins^(C)
Hi-Z
Hi-Z
9
2
3
Config
RESET STATE
7
BTMODE[11]^(B)
5
5
A. Power supplies and DEV_CLKIN/AUX_CLKIN must be stable before the start of t_w(RESET).
B. RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.
C. For more detailed information on the RESET STATE of each pin, see Section 7.3.17, Pin Behaviors at Reset. Also
see Section 3.2, Terminal Functions for the IPU/IPD settings during reset.
Figure 7-4. Power-Up Timing
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Power, Reset, Clocking, and Interrupts 195
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