TMS320DM8148_17 Datasheet, PDF (275/377 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
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8.10.1 HDVPSS Electrical Data/Timing
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
Table 8-42. Timing Requirements for HDVPSS Input
(see Figure 8-38 and Figure 8-39)
NO.
VIN[X]A_CLK
1 t_c(CLK)
2 t_w(CLKH)
3 t_w(CLKH)
t_su(DE-CLK)
t_{su(VSYNC-CLK)}
4 t_su(FLD-CLK)
t_{su(HSYNC-CLK)}
t_su(D-CLK)
t_h(CLK-DE)
t_h(CLK-VSYNC)
5 t_h(CLK-FLD)
t_h(CLK-HSYNC)
t_h(CLK-D)
Cycle time, VIN[x]A_CLK
Pulse duration, VIN[x]A_CLK high (45% of t_c)
Pulse duration, VIN[x]A_CLK low (45% of t_c)
Input setup time, control valid to VIN[x]A_CLK high/low
Input setup time, data valid to VIN[x]A_CLK high/low
Input hold time, control valid from VIN[x]A_CLK high/low
Input hold time, data valid from VIN[x]A_CLK high/low
VIN[x]B_CLK
1 t_c(CLK)
2 t_w(CLKH)
3 t_w(CLKH)
t_su(DE-CLK)
t_{su(VSYNC-CLK)}
4 t_su(FLD-CLK)
t_{su(HSYNC-CLK)}
t_su(D-CLK)
t_h(CLK-DE)
t_h(CLK-VSYNC)
5 t_h(CLK-FLD)
t_h(CLK-HSYNC)
t_h(CLK-D)
Cycle time, VIN[x]B_CLK
Pulse duration, VIN[x]B_CLK high (45% of t_c)
Pulse duration, VIN[x]B_CLK low (45% of t_c)
Input setup time, control valid to VIN[x]B_CLK high/low
Input setup time, data valid to VIN[x]B_CLK high/low
Input hold time, control valid from VIN[x]B_CLK high/low
Input hold time, data valid from VIN[x]B_CLK high/low
(1) For maximum frequency of 165 MHz.
OPP100/120/166
UNIT
MIN
MAX
6.06 ⁽¹⁾
ns
2.73
ns
2.73
ns
3
ns
3
0.1
ns
0.1
6.06 ⁽¹⁾
ns
2.73
ns
2.73
ns
3
ns
3
0.1
ns
0.1
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Peripheral Information and Timings 275
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