TMS320DM8148_17 Datasheet, PDF (237/377 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
www.ti.com
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
Table 8-14. Ethernet MAC Switch Registers (continued)
ARM/L3 MASTERS
EMAC HEX
ADDRESS RANGE
0x4A10 003C
0x4A10 0040
0x4A10 0050
0x4A10 0054
0x4A10 0058
0x4A10 005C
0x4A10 0060
0x4A10 0064
0x4A10 0068
0x4A10 006C
0x4A10 0070
0x4A10 0074
0x4A10 0078
0x4A10 007C – 0x4A10 008C
0x4A10 0090
0x4A10 0094
0x4A10 0098
0x4A10 009C
0x4A10 00A0
0x4A10 00A4
0x4A10 00A8
0x4A10 00AC
0x4A10 00B0
0x4A10 00B4
0x4A10 00B8
0x4A10 00BC – 0x4A10 00FC
0x4A10 0100
0x4A10 0104
0x4A10 0108
0x4A10 010C
0x4A10 0110
0x4A10 0114
0x4A10 0118
0x4A10 011C
0x4A10 0120
0x4A10 0124
0x4A10 0128
0x4A10 012C
0x4A10 0130
0x4A10 0134
0x4A10 0138
0x4A10 013C
0x4A10 0140
0x4A10 0144
ACRONYM
REGISTER NAME
CPDMA_TX_PRI_MAP
CPDMA_RX_CH_Map
P1_MAX_BLKS
P1_BLK_CNT
P1_TX_IN_CTL
P1_PORT_VLAN
P1_TX_PRI_MAP
P1_TS_CTL
P1_TS_SEQ_LTYPE
P1_TS_VLAN
SL1_SA_LO
SL1_SA_HI
P1_SEND_PERCENT
–
P2_MAX_BLKS
P2_BLK_CNT
P2_TX_IN_CTL
P2_PORT_VLAN
P2_TX_PRI_MAP
P2_TS_CTL
P2_TS_SEQ_LTYPE
P2_TS_VLAN
SL2_SA_LO
SL2_SA_HI
P2_SEND_PERCENT
–
TX_IDVER
TX_CONTROL
TX_TEARDOWN
–
RX_IDVER
RX_CONTROL
RX_TEARDOWN
SOFT_RESET
DMACONTROL
DMASTATUS
RX_BUFFER_OFFSET
EMCONTROL
TX_PRI0_RATE
TX_PRI1_RATE
TX_PRI2_RATE
TX_PRI3_RATE
TX_PRI4_RATE
TX_PRI5_RATE
CPSW CPDMA TX (Port 0 Rx) Packet Priority to Header Priority Mapping
Register
CPSW CPDMA RX (Port 0 Tx) Switch Priority to DMA Channel Mapping
Register
CPSW Port 1 Maximum FIFO Blocks Register
CPSW Port 1 FIFO Block Usage Count (Read Only)
CPSW Port 1 Transmit FIFO Control
CPSW Port 1 VLAN Register
CPSW Port 1 Tx Header Priority to Switch Priority Mapping Register
CPSW_3GF Port 1 Time Sync Control Register
CPSW_3GF Port 1 Time Sync LTYPE (and SEQ_ID_OFFSET)
CPSW_3GF Port 1 Time Sync VLAN2 and VLAN2 Register
CPSW CPGMAC_SL1 Source Address Low Register
CPSW CPGMAC_SL1 Source Address High Register
CPSW Port 1 Transmit Queue Send Percentages
Reserved
CPSW Port 2 Maximum FIFO Blocks Register
CPSW Port 2 FIFO Block Usage Count (Read Only)
CPSW Port 2 Transmit FIFO Control
CPSW Port 2 VLAN Register
CPSW Port 2 Tx Header Priority to Switch Priority Mapping Register
CPSW_3GF Port 2 Time Sync Control Register
CPSW_3GF Port 2 Time Sync LTYPE (and SEQ_ID_OFFSET)
CPSW_3GF Port 2 Time Sync VLAN2 and VLAN2 Register
CPSW CPGMAC_SL2 Source Address Low Register
CPSW CPGMAC_SL2 Source Address High Register
CPSW Port 2 Transmit Queue Send Percentages
Reserved
CPDMA_REGS TX Identification and Version Register
CPDMA_REGS TX Control Register
CPDMA_REGS TX Teardown Register
Reserved
CPDMA_REGS RX Identification and Version Register
CPDMA_REGS RX Control Register
CPDMA_REGS RX Teardown Register
CPDMA_REGS Soft Reset Register
CPDMA_REGS CPDMA Control Register
CPDMA_REGS CPDMA Status Register
CPDMA_REGS Receive Buffer Offset
CPDMA_REGS Emulation Control
CPDMA_REGS Transmit (Ingress) Priority 0 Rate
CPDMA_REGS Transmit (Ingress) Priority 1 Rate
CPDMA_REGS Transmit (Ingress) Priority 2 Rate
CPDMA_REGS Transmit (Ingress) Priority 3 Rate
CPDMA_REGS Transmit (Ingress) Priority 4 Rate
CPDMA_REGS Transmit (Ingress) Priority 5 Rate
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Peripheral Information and Timings 237
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