TMS320DM8148_17 Datasheet, PDF (257/377 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
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SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
8.8.2 GPMC Electrical Data/Timing
8.8.2.1 GPMC/NOR Flash Interface Synchronous Mode Timing (Non-Multiplexed and Multiplexed Modes)
Table 8-34. Timing Requirements for GPMC/NOR Flash Interface - Synchronous Mode
(see Figure 8-21, Figure 8-22, Figure 8-23 for Non-Multiplexed Modes)
(see Figure 8-24, Figure 8-25, Figure 8-26 for Multiplexed Modes)
OPP100/120/166
NO.
MIN
MAX
13 t_su(DV-CLKH)
Setup time, read GPMC_D[15:0] valid before GPMC_CLK high
4
14 t_h(CLKH-DV)
Hold time, read GPMC_D[15:0] valid after GPMC_CLK high
3
22 t_{su(WAITV-CLKH)}
Setup time, GPMC_WAIT[x] valid before GPMC_CLK high
4
23 t_{h(CLKH-WAITV)}
Hold time, GPMC_WAIT[x] valid after GPMC_CLK high
3
UNIT
ns
ns
ns
ns
Table 8-35. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash
Interface - Synchronous Mode
(see Figure 8-21, Figure 8-22, Figure 8-23 for Non-Multiplexed Modes)
(see Figure 8-24, Figure 8-25, Figure 8-26 for Multiplexed Modes)
NO
.
1 t_c(CLK)
2 ^tw(CLKH)
t_w(CLKL)
3 t_d(CLKH-nCSV)
4 t_{d(CLKH-nCSIV)}
PARAMETER
Cycle time, output clock GPMC_CLK period
Pulse duration, output clock GPMC_CLK high
Pulse duration, output clock GPMC_CLK low
Delay time, GPMC_CLK rising edge to GPMC_CS[x] transition
Delay time, GPMC_CLK rising edge to GPMC_CS[x] invalid
MUX0 and Non-Multi
Muxed pins
OPP100/120/166
MIN
20 ⁽¹⁾
0.5P ⁽²⁾
0.5P ⁽²⁾
F - 3 ⁽³⁾
E - 3 ⁽⁴⁾
MAX
F + 6 ⁽³⁾
E + 6⁽⁴⁾
UNIT
ns
ns
ns
ns
B - 6 ⁽⁵⁾
B + 6⁽⁵⁾
5 t_d(ADDV-CLK)
Delay time, GPMC_A[27:0] address bus valid to
GPMC_CLK first edge
MUX1 for
GPMC_A[15:0]
MUX1/2 for
GPMC_A[27:20]
GPMC_AD[15:0]
B - 10⁽⁵⁾
B - 10⁽⁵⁾
B - 10⁽⁵⁾
B + 6⁽⁵⁾
ns
B + 6⁽⁵⁾
B + 6⁽⁵⁾
MUX0 and Non-Multi
Muxed pins
-3
6 t_{d(CLKH-ADDIV)}
MUX1 for
Delay time, GPMC_CLK rising edge to GPMC_A[27:0] _{GPMC_A[15:0]}
GPMC address bus invalid
MUX1/2 for
GPMC_A[27:20]
-6
ns
-6
7 t_d(nBEV-CLK)
GPMC_AD[15:0]
Delay time, GPMC_BE0_CLE, GPMC_BE1 valid to GPMC_CLK first edge
-6
B - 3⁽⁵⁾
B + 3⁽⁵⁾ ns
(1) Sync mode can operate at 50 MHz max.
(2) P = GPMC_CLK period.
(3) For nCS falling edge (CS activated):
• For GpmcFCLKDivider = 0:
F = 0.5 * CSExtraDelay * GPMC_FCLK
• For GpmcFCLKDivider = 1:
F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are
even)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise
• For GpmcFCLKDivider = 2:
F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
(4) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(5) B = ClkActivationTime * GPMC_FCLK
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