LP2975 Datasheet, PDF (29/37 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

LP2975
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SNVS006F – SEPTEMBER 1997 – REVISED APRIL 2013
GENERAL DESIGN PROCEDURE
Assuming that V_IN, V_OUT, and R_L are defined:
1. Calculate the required value of capacitance for C_OUT so that the pole f_p ≤ 200 Hz (see previous section,
Output Capacitor. For this calculation, an ESR of about 0.1Ω can be assumed for the purpose of determining
C_OUT.
IMPORTANT: If a smaller value of output capacitor is used (so that the value of f_p >200 Hz), the phase
margin of the control loop will be reduced. This will result in increased ringing on the output voltage during a
load transient. If the output capacitor is made extremely small, oscillations will result.
To illustrate this effect, scope photos have been presented showing the output voltage of reference design
#2 as the output capacitor is reduced to approximately 1/30 of the nominal value (the value which sets f_p =
200 Hz). As shown, the effect of deviating from the nominal value is gradual and the regulator is quite robust
in resisting going into oscillations.
2. Approximate the crossover frequency f_c using the equation in the previous section Crossover Frequency and
Phase Margin.
3. Calculate the required ESR of the output capacitor so that the frequency of the zero f_z is set to 0.5 f_c (see
previous section, Output Capacitor).
4. Calculate the value of the feed-forward capacitor C_F so that the zero f_zf occurs at the frequency which yields
the maximum phase gain for the output voltage selected (see previous section, LOW OUTPUT VOLTAGE
AND C_F). The formula for calculating C_F is in the previous section, Feed-Forward Capacitor.
Lower ESR electrolytics are available which use organic electrolyte (OSCON types), but are more costly than
typical aluminum electrolytics.
If the calculated value of ESR is higher than what is found in the selected capacitor, an external resistor can be
placed in series with C_OUT.
LOW VOLTAGE DESIGNS: Designs which have a low output voltage (where the positive effects of C_F are very
small) may be marginally stable if the C_OUT and ESR values are not carefully selected.
Also, if the FET gate capacitance is large (as in the case of a high-current FET), the pole f_pg could possibly get
low enough in frequency to cause a problem.
The solution in both cases is to increase the amount of output capacitance which will shift f_p to a lower frequency
(and reduce overall loop bandwidth). The ESR and C_F calculations should be repeated, since this changes the
crossover frequency f_c.
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