LP2975 Datasheet, PDF (18/37 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

LP2975
SNVS006F – SEPTEMBER 1997 – REVISED APRIL 2013
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C_OUT forms a pole (referred to as f_p) in conjuction with the load resistance which causes the loop gain to roll off
(decrease) at an additional −20 dB/decade. The frequency of the pole is:
f_p = 0.16 / [ (R_L + ESR) × C_OUT]
where
• R_L is the load resistance.
• C_OUT is the value of the output capacitor.
• ESR is the equivalent series resistance of C_OUT.
As a general guideline, the frequency of f_p should be ≤ 200 Hz. It should be noted that higher load currents
correspond to lower values of R_L, which requires that C_OUT be increased to keep f_p at a given frequency.
DESIGN EXAMPLE: Select the minimum required output capacitance for a design whose output specifications
are 5V @ 1A:
f_p = 0.16 / [ (R_L + ESR) × C_OUT]
Re-written:
C_OUT = 0.16 / [f_p × (R_L + ESR) ]
Values used for the calculation:
f_p = 200 Hz, R_L = 5Ω, ESR = 0.1Ω (assumed).
Solving for C_OUT, we get 157 μF (nearest standard size would be 180 μF).
The ESR of the output capacitor is very important for stability, as it creates a zero (f_z) which cancels much of the
phase shift resulting from one of the poles present in the loop. The frequency of the zero is calculated from:
f_z = 0.16 / (ESR × C_OUT)
For best results in most designs, the frequency of f_z should fall between 5 kHz and 50 kHz. It must be noted that
the values of C_OUT and ESR usually vary with temperature (severely in the case of aluminum electrolytics), and
this must be taken into consideration.
For the design example (V_OUT = 5V @ 1A), select a capacitor which meets the f_z requirements. Solving the
equation for ESR yields:
ESR = 0.16 / (f_z × C_OUT)
Assuming f_z = 5 kHz and 50 kHz, the limiting values of ESR for the 180 μF capacitor are found to be:
18 mΩ ≤ ESR ≤ 0.18Ω
A good-quality, low-ESR capacitor type such as the Panasonic HFQ is a good choice. However, the 10V/180 µF
capacitor (#ECA-1AFQ181) has an ESR of 0.3Ω which is not in the desired range.
To assure a stable design, some of the options are:
1. Use a different type capacitor which has a lower ESR such as an organic-electrolyte OSCON.
2. Use a higher voltage capacitor. Since ESR is inversely proportional to the physical size of the capacitor, a
higher voltage capacitor with the same C value will typically have a lower ESR (because of the larger case
size). In this example, a Panasonic ECA-1EFQ181 (which is a 180 µF/25V part) has an ESR of 0.17Ω and
would meet the desired ESR range.
3. Use a feed-forward capacitor (see next section).
Feed-Forward Capacitor
Although not required in every application, the use of a feed-forward capacitor (C_F) can yield improvements in
both phase margin and transient response in most designs.
The added phase margin provided by C_F can prevent oscillations in cases where the required value of C_OUT and
ESR can not be easily obtained (see previous section).
C_F can also reduce the phase shift due to the pole resulting from the Gate capacitance, stabilizing applications
where this pole occurs at a low frequency (before cross-over) which would cause oscillations if left
uncompensated (see later section, Gate Capacitance Pole Frequency (f_pg).
Even in a stable design, adding C_F will typically provide more optimal loop response (faster settling time). For
these reasons, the use of a feed-forward capacitor is always recommended.
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