LP2975 Datasheet, PDF (14/37 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

LP2975
SNVS006F – SEPTEMBER 1997 – REVISED APRIL 2013
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Figure 21. Transient Response for 0–6A Load Step
Application Hints
SELECTING THE FET
The best choice of FET for a specific application will depend on a number of factors:
VOLTAGE RATING: The FET must have a Drain-to-Source breakdown voltage (sometimes called BV_DSS) which
is greater than the input voltage.
DRAIN CURRENT: On-state Drain current must be specified to be greater than the worst-case (short circuit)
load current for the application.
TURN-ON THRESHOLD: The Gate-to-Source voltage where the FET turns on (called the Gate Threshold
Voltage) is very important. Many FET's are intended for use with G-to-S voltages in the 5V to 10V range. These
should only be used in applications where the input voltage is high enough to provide >5V of drive to the Gate.
Newer FET's are becoming available with lower turn-on thresholds (Logic-Level FET's) which turn on fully with a
gate voltage of only 3V to 4V. Low threshold FET's should be used in applications where the input voltage is ≤
5V.
ON RESISTANCE: FET on resistance (often called R_DSON) is a critical parameter since it directly determines the
minimum input-to-output voltage required for operation at a given load current (also called dropout voltage).
R_DSON is highly dependent on the amount of Gate-to-Source voltage applied. For example, the R_DSON of a FET
with V_G-S = 5V will typically decrease by about 25% as the V_G-S is increased to 10V. R_DSON is also temperature
dependent, increasing at higher temperatures.
The dropout voltage of any LDO design is directly related to R_DSON, as given by:
V_DROPOUT = I_LOAD × (R_DSON + R_SC)
where
• R_SC is the short-circuit current limit set resistor (see TYPICAL APPLICATION CIRCUITS)
GATE CAPACITANCE: Selecting a FET with the lowest possible Gate capacitance improves LDO performance
in two ways:
1. The Gate pin of the LP2975 (which drives the Gate of the FET) has a limited amount of current to source or
sink. This means faster changes in Gate voltage (which corresponds to faster transient response) will occur
with a smaller amount of Gate capacitance.
2. The Gate capacitance forms a pole in the loop gain which can reduce phase margin. When possible, this
pole should be kept at a higher frequency than the cross-over frequency of the regulator loop (see later
section, Crossover Frequency and Phase Margin).
A high value of Gate capacitance may require that a feedforward capacitor be used to cancel some of the excess
phase shift (see later section, Feed-Forward Capacitor) to prevent loop instability.
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