LP2975 Datasheet, PDF (15/37 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

LP2975
www.ti.com
SNVS006F – SEPTEMBER 1997 – REVISED APRIL 2013
POWER DISSIPATION: The maximum power dissipated in the FET in any application can be calculated from:
P_MAX = (V_IN − V_OUT) × I_MAX
where
• I_MAX is the maximum output current
It should be noted that if the regulator is to be designed to withstand short-circuit, a current sense resistor must
be used to limit I_MAX to a safe value (refer to section SHORT-CIRCUIT CURRENT LIMITING).
The power dissipated in the FET determines the best choice for package type. A TO-220 package device is best
suited for applications where power dissipation is less than 15W. Power levels above 15W would almost certainly
require a TO-3 type device.
In low power applications, surface-mount package devices are size-efficient and cost-effective, but care must be
taken to not exceed their power dissipation limits.
POWER DISSIPATION AND HEATSINKING
Since the LP2975 controller is suitable for use with almost any external P-FET, it follows that designs can be built
which have very high power dissipation in the pass FET. Since the controller can not protect the FET from
overtemperature damage, thermal design must be carefully done to assure a reliable design.
THERMAL DESIGN METHOD: The temperature of the FET and the power dissipated is defined by the equation:
T_J = (θ_J-A × P_D) + T_A
where
• T_J is the junction temperature of the FET.
• T_A is the ambient temperature.
• P_D is the power dissipated by the FET.
• θ_J-A is the junction-to-ambient thermal resistance.
To ensure a reliable design, the following guidelines are recommended:
1. Design for a maximum (worst-case) FET junction temperature which does not exceed 150°C.
2. Heatsinking should be designed for worst-case (maximum) values of T_A and P_D.
3. In designs which must survive a short circuit on the output, the maximum power dissipation must be
calculated assuming that the output is shorted to ground:
P_D(MAX) = V_IN × I_SC
where
• I_SC is the short-circuit output current.
4. If the design is not intended to be short-circuit proof, the maximum power dissipation for intended operation
will be:
P_D(MAX) = (V_IN − V_OUT) × I_MAX
where
• I_MAX is the maximum output current.
LOW POWER (<2W) APPLICATIONS: In most cases, some type of small surface-mount device will be used for
the FET in low power designs. Because of the increased cell density (and tiny packages) used by modern FET's,
the current carrying capability may easily exceed the power dissipation limits of the package. It is possible to
parallel two or more FET's, which divides the power dissipation among all of the packages.
It should be noted that the “heatsink” for a surface mount package is the copper of the PC board and the
package itself (direct radiation).
Surface-mount devices have the value of θ_J-A specified for a typical PC board mounting on their data sheet. In
most cases it is best to start with the known data for the application (P_D, T_A, T_J) and calculate the required value
of θ_J-A needed. This value will define the type of FET and, possibly, the heatsink required for cooling.
θ_J-A = (T_J − T_A)/P_D(MAX)
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