LP2975 Datasheet, PDF (12/37 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

LP2975
SNVS006F – SEPTEMBER 1997 – REVISED APRIL 2013
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The effect of reducing C_OUT is to decrease phase margin. As phase margin is decreased, the output ringing will
increase when a load step is applied to the output. Eventually, if C_OUT is made small enough, the regulator will
oscillate.
To demonstrate these effects, the value of C_OUT in reference design #2 is halved by removing one of the two 68
µF output capacitors and the transient response test is repeated (see photo below). The total overshoot
increases from −50 mV to about −75 mV, and the second “ring” on the transient is noticeably larger.
Figure 19. Transient Response with Output Capacitor Halved
The design is next tested with only a 4.7 µF output capacitor (see scope photo below). Observe that the vertical
scale has been increased to 100 mV/division to accommodate the −250 mV undershoot. More important is the
severe ringing as the transient decays. Most designers would recognize this immediately as the warning sign of a
marginally stable design.
Figure 20. Transient Response with Only 4.7 µF Output Cap
The reason this design is marginally stable is that the 4.7 µF output capacitor (along with the 6Ω output load)
sets the pole f_p at 5 kHz. Analysis shows that the unity-gain frequency of the loop is increased to about 100 kHz,
allowing the FET's gate capacitance pole f_pg to cause significant phase shift before the loop gain goes below
unity. Also, because of the low output voltage, the feedforward capacitor provides less than 10° of positive phase
shift. For good stability, the output capcitor needs to be larger than 4.7 µF.
For detailed information on stability and phase margin, see the Application Hints section.
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