LP2975 Datasheet, PDF (21/37 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

LP2975
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SNVS006F – SEPTEMBER 1997 – REVISED APRIL 2013
It is important to note that R_O is a function of input supply voltage (see Figure 22. As shown, the minimum value
of R_O is about 550Ω @ V_IN = 24V, increasing to about 1.55 kΩ @ V_IN = 3V.
Using the equation for f_pg, a family of curves are provided showing how f_pg varies with C_EFF for several values of
R_O (see Figure 23).
Figure 23. f_pg vs. C_EFF
As can be seen in the graph, values of C_EFF in the 500 pF–2500 pF range produce values for f_pg between 40 kHz
and 700 kHz. To determine what effect f_pg will have on stability, the bandwidth of the regulator loop must be
calculated (see next section, Crossover Frequency and Phase Margin).
Crossover Frequency and Phase Margin
The term f_c will be used to define the crossover frequency of the regulator loop (which is the frequency where the
gain curve crosses the 0 dB axis). The importance of this frequency is that it is the point where the loop gain
goes below unity, which marks the usable bandwidth of the regulator loop.
It is the phase margin (or lack of it) at f_c that determines whether the regulator is stable. Phase margin is defined
as the total phase shift subtracted from 180°. In general, a stable loop requires at least 20°-30° of phase margin
at f_c.
f_c can be approximated by the following equation (all terms have been previously defined):
This equation assumes that no C_F is used and f_pg/f_c > 1.
If the frequency of the Gate capacitance pole f_pg has been calculated (previous section), the amount of added
phase shift may now be determined. As shown in the graph below (see Figure 24, the amount of added phase
shift increases as f_pg approaches f_c.
The amount of phase shift due to f_pg that can occur before oscillation takes place depends on how much added
phase shift is present as a result of the C_OUT pole (see previous section, Output Capacitor).
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