LP2975 Datasheet, PDF (24/37 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

LP2975
SNVS006F – SEPTEMBER 1997 – REVISED APRIL 2013
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Figure 26. Effects of a Single Zero
Stability Analysis of Typical Applications
The first application to be analyzed is a fixed-output voltage regulator with no feed-forward capacitor (see
Figure 27).
Figure 27. Stable Plot without Feed-Forward
In this example, the value of C_OUT is selected so that the pole formed by C_OUT and R_L (previously defined as f_p)
is set at 200 Hz. The ESR of C_OUT is selected so that zero formed by the ESR and C_OUT (defined as f_z) is set at 5
kHz (these selections follow the general guidelines stated previously in this document). Note that the gate
capacitance is assumed to be moderate, with the pole formed by the C_GATE (defined as f_pg) occurring at 100 kHz.
To estimate the total phase margin, the individual phase shift contributions of each pole and zero will be
calculated assuming f_p = 200 Hz, f_z = 5 kHz, f_c = 10 kHz and f_pg = 100 kHz:
Controller pole shift = −90°
f_p shift = −arctan (10k/200) = −89°
f_z shift = arctan (10k/5k) = +63°
f_pg shift = −arctan (10k/100k) = −6°
Summing the four numbers, the estimate for the total phase shift is −122°, which corresponds to a phase
margin of 58°. This application is stable, but could be improved by using a feed-forward capacitor (see next
section).
EFFECT OF FEED-FORWARD: The example previously used will be continued with the addition of a feed-
forward capacitor C_F (see Figure 28). The zero formed by C_F (previously defined as f_zf) is set at 10 kHz and the
pole formed by C_F (previously defined as f_pf) is set at 40 kHz (the 4X ratio of f_pf/f_zf corresponds to V_OUT = 5V).
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