LP2975 Datasheet, PDF (20/37 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

LP2975
SNVS006F – SEPTEMBER 1997 – REVISED APRIL 2013
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Gate Capacitance
An important consideration of a design is to identify the frequency of the pole which results from the capacitance
of the Gate of the FET (this pole will be referred to as f_pg). As f_pg gets closer to the loop crossover frequency, the
phase margin is reduced. Information will now be provided to allow the total Gate capacitance to be calculated so
that f_pg can be approximated.
The first step in calculating fp is to determine how much effective Gate capacitance (C_EFF) is present. The
formula for calculating C_EFF is:
C_EFF = C_GS + C_GD [1 + G_m (R_L / / ESR) ]
where
• C_GS is the Gate-to-Source capacitance, which is found from the values (refer to FET data sheet for values of
C_ISS and C_RSS):
C_GS = C_ISS − C_RSS
where
• G_GD is the Gate-to-Drain capacitance, which is equal to:
C_GD = C_RSS
where
• G_m is the transconductance of the FET.
The FET data sheet specifies forward transconductance (G_fs) at some value of drain current (defined as I_D). To
find Gm at the desired value of load current (defined as I_L), use the formula:
G_m = G_fs × (I_L / I_D)^1/2
where
• R_Lis the load resistance.
ESR is the equivalent series resistance of the output capacitor.
• The term R_L / / ESR is defined as:
(R_L × ESR) / (R_L + ESR)
It can be seen from these equations that C_EFF varies with R_L. To get the worst-case (maximum) value for C_EFF,
use the maximum value of load current, which also means the minimum value of load resistance R_L. It should be
noted that in most cases, the ESR is the dominant term which determines the value of R_L / / ESR.
Figure 22. Gate Pin Output Impedance
Gate Capacitance Pole Frequency (f_pg)
The pole frequency resulting from the Gate capacitance C_EFF is defined as f_pg and can be approximated from:
f_pg ≃ 0.16 / (R_O × C_EFF)
where
• R_O is the output impedance of the LP2975 Gate pin which drives the Gate of the FET.
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