LP2975 Datasheet, PDF (28/37 Pages) National Semiconductor (TI) – MOSFET LDO Driver/Controller

LP2975
SNVS006F – SEPTEMBER 1997 – REVISED APRIL 2013
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Figure 33. Phase Lead Provided by C_F
The most important information on the graph is the frequency range of f_zf which will provide the maximum benefit
(most positive phase shift):
For V_OUT = 12V: 0.1 f_c < f_z < 1.0 f_c
For V_OUT = 5V: 0.2 f_c < f_z < 1.2 f_c
For V_OUT = 3.3V: 0.2 f_c < f_z < 1.3 f_c
It's also important to note how the maximum available phase shift that C_F can provide drops off with V_OUT. At
12V, more than 50° can be obtained, but at 3.3V less than 30° is possible. The lesson from this is that higher
voltage designs are more tolerant of phase shifts from both f_pg (the gate capacitance pole) and incorrect
placement of f_z (which means the output capacitor ESR is not at its nominal value). At lower values of V_OUT,
these parameters must be more precisely selected since C_F can not provide as much correction.
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