DS90CF366_16 Datasheet, PDF (26/38 Pages) Texas Instruments – DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz

DS90CF366, DS90CF386
SNLS055J – NOVEMBER 1999 – REVISED MAY 2016
www.ti.com
9 Power Supply Recommendations
Proper power supply decoupling is important to ensure a stable power supply with minimal power supply noise.
Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a
conservative approach, three parallel-connected decoupling capacitors (multi-layered ceramic type in surface
mount form factor) between each V_CC (V_CC, PLL V_CC, LVDS V_CC) and the ground plane(s) are recommended.
The three capacitor values are 0.1 μF, 0.01 μF, and 0.001 μF. The preferred capacitor size is 0402. An example
is shown in Figure 28. The designer should employ wide traces for power and ground and ensure each capacitor
has its own via to the ground plane. This helps to reduce overall inductance with regards to power supply
filtering. If board space is limiting the number of bypass capacitors, the PLL V_CC should receive the most filtering.
Next would be the LVDS V_CC pins and finally the logic V_CC pins.
Figure 28. Recommended Bypass Capacitor Decoupling
Configuration for V_CC, PLL V_CC, and LVDS V_CC
10 Layout
10.1 Layout Guidelines
As with any high speed design, board designers must maximize signal integrity by limiting reflections and
crosstalk that can adversely affect high frequency and EMI performance. The following practices are
recommended layout guidelines to optimize device performance.
• Ensure that differential pair traces are always closely coupled to eliminate noise interference from other
signals and take full advantage of the common mode noise canceling effect of the differential signals.
• Maintain equal length on signal traces for a given differential pair.
• Limit impedance discontinuities by reducing the number of vias on signal traces.
• Eliminate any 90º angles on traces and use 45º bends instead.
• If a via must exist on one signal polarity, mirror the via implementation on the other polarity of the differential
pair.
• Match the differential impedance of the selected physical media. This impedance should also match the value
of the termination resistor that is connected across the differential pair at the receiver's input.
• When possible, use short traces for LVDS inputs.
10.2 Layout Examples
The following images show an example layout of the DS90CF386. Traces in blue correspond to the top layer and
the traces in green correspond to the bottom layer. Note that differential pair inputs to the DS90CF386 are tightly
coupled and close to the connector pins. In addition, observe that the power supply decoupling capacitors are
placed as close as possible to the power supply pins with through vias in order to minimize inductance. The
principles illustrated in this layout can also be applied to the 48-pin DS90CF366.
26
Submit Documentation Feedback
Copyright © 1999–2016, Texas Instruments Incorporated
Product Folder Links: DS90CF366 DS90CF386