DS90CF366_16 Datasheet, PDF (11/38 Pages) Texas Instruments – DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz

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Timing Diagrams (continued)
DS90CF366, DS90CF386
SNLS055J – NOVEMBER 1999 – REVISED MAY 2016
Device Pin Name Signal
Signal Pattern
Signal Frequency
TxCLK IN / RxCLK OUT
Dot Clk
f
TxIN0 / RxOUT0
R0
f / 16
TxIN1 / RxOUT1
R1
f/8
TxIN2 / RxOUT2
R2
f/4
TxIN3 / RxOUT3
R3
f/2
TxIN4 / RxOUT4
R4
Steady State, Low
TxIN5 / RxOUT5
R5
Steady State, Low
TxIN6 / RxOUT6
G0
f / 16
TxIN7 / RxOUT7
G1
f/8
TxIN8 / RxOUT8
G2
f/4
TxIN9 / RxOUT9
G3
f/2
TxIN10 / RxOUT10
G4
Steady State, Low
TxIN11 / RxOUT11
G5
Steady State, Low
TxIN12 / RxOUT12
B0
f / 16
TxIN13 / RxOUT13
B1
f/8
TxIN14 / RxOUT14
B2
f/4
TxIN15 / RxOUT15
B3
f/2
TxIN16 / RxOUT16
B4
Steady State, Low
TxIN17 / RxOUT17
B5
Steady State, Low
TxIN18 / RxOUT18
HSYNC
Steady State, High
TxIN19 / RxOUT19
VSYNC
Steady State, High
TxIN20 / RxOUT20
ENA
Steady State, High
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O, and CMOS or LVCMOS I/O.
(2) The 16 grayscale test pattern tests device power consumption for a typical LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 1 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 3. Test Pattern, 16 Grayscale (DS90CF366)
Figure 4. DS90CF3x6 (Receiver) CMOS or LVCMOS Output Load and Transition Times
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