DS90CF366_16 Datasheet, PDF (19/38 Pages) Texas Instruments – DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz

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DS90CF366, DS90CF386
SNLS055J – NOVEMBER 1999 – REVISED MAY 2016
7.4 Device Functional Modes
7.4.1 Power Sequencing and Power-Down Mode
The DS90CF386 and DS90CF366 may be placed into a power down mode at any time by asserting the PWR
DWN pin (active low). The DS90CF386 and DS90CF366 are also designed to protect themselves from
accidental loss of power to either the transmitter or receiver. If power to the transmit board is lost, the receiver
clocks (input and output) stop. The data outputs (RxOUT) retain the states they were in when the clocks stopped.
When the receiver board loses power, the receiver inputs are controlled by a failsafe bias circuitry. The LVDS
inputs are High-Z during initial power on and power off conditions. Current is limited to 5 mA per input, thus
avoiding the potential for latch-up when powering the device.
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