DS90CF366_16 Datasheet, PDF (22/38 Pages) Texas Instruments – DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz

DS90CF366, DS90CF386
SNLS055J – NOVEMBER 1999 – REVISED MAY 2016
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• H_Blank = Blanking Period Horizontal Lines
• V_Active = Active Display Vertical Lines
• V_Blank = Blanking Period Vertical Lines
• f_Vertical = Refresh Rate (in Hz)
• f_Clk = Operating Frequency of LVDS clock
(1)
In each frame, there is a blanking period associated with horizontal rows and vertical columns that are not
actively displayed on the panel. These blanking period pixels must be included to determine the required clock
frequency. Consider the following example to determine the required LVDS clock frequency:
• H_Active = 640
• H_Blank = 40
• V_Active = 480
• V_Blank = 41
• f_Vertical = 59.95 Hz
Thus, the required operating frequency is determined with Equation 2.
[640 + 40] × [480 + 41] × 59.95 = 21239086 Hz ≈ 21.24 MHz
(2)
Since the operating frequency for the PLL in the DS90CF386 and DS90CF366 ranges from 20 to 85 MHz, the
DS90CF386 and DS90CF366 can support a panel display with the aforementioned requirements.
If the specific blanking interval is unknown, the number of pixels in the blanking interval can be approximated to
20% of the active pixels. Equation 3 can be used as a conservative approximation for the operating LVDS clock
frequency:
f_Clk ≈ H_Active × V_Active × f_Vertical × 1.2
(3)
Using this approximation, the operating frequency for the example in this section is estimated with Equation 4.
640 × 480 × 59.95 × 1.2 = 22099968 Hz ≈ 22.10 MHz
(4)
8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display
Ensure that the LVCMOS outputs are mapped to align with the endpoint display RGB mapping requirements
following the deserializer. See the following for two popular mapping topologies for 8-bit RGB data.
1. LSBs are mapped to RxIN3±.
2. MSBs are mapped to RxIN3±.
Table 2 and Table 3 depict how these two popular topologies can be mapped to the DS90CF386 outputs.
LVDS INPUT
CHANNEL
RxIN0
RxIN1
Table 2. 8-Bit Color Mapping with LSBs on RxIN3±
LVDS BIT STREAM
POSITION
TxIN0
TxIN1
TxIN2
TxIN3
TxIN4
TxIN6
TxIN7
TxIN8
TxIN9
TxIN12
TxIN13
TxIN14
TxIN15
TxIN18
LVCMOS OUTPUT
CHANNEL
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT18
COLOR MAPPING
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
COMMENTS
MSB
MSB
22
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