DS90CF366_16 Datasheet, PDF (17/38 Pages) Texas Instruments – DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz

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7 Detailed Description
DS90CF366, DS90CF386
SNLS055J – NOVEMBER 1999 – REVISED MAY 2016
7.1 Overview
The DS90CF386 is a receiver that converts four LVDS (Low Voltage Differential Signaling) data streams into
parallel 28 bits of LVCMOS data (24 bits of RGB and 4 bits of HSYNC, VSYNC, DE, and CNTL). The
DS90CF366 is a receiver that converts three LVDS data streams into parallel 21 bits of LVCMOS data (18 bits of
RGB and 3 bits of HSYNC, VSYNC, and DE). An internal PLL locks to the incoming LVDS clock ranging from 20
to 85 MHz. The locked PLL ensures a stable clock to sample the output LVCMOS data on the Receiver Clock
Out falling edge. These devices feature a PWR DWN pin to put the device into low power mode when there is no
active input data.
7.2 Functional Block Diagrams
100 Ÿ
4 x LVDS Data
(140 to 595 Mbps on
Each LVDS Channel)
100 Ÿ
100 Ÿ
28 x LVCMOS
Outputs
100 Ÿ
LVDS Clock
(20 to 85 MHz)
100 Ÿ
PLL
Receiver Clock Out
PWR DWN
Copyright © 2016, Texas Instruments Incorporated
Figure 18. DS90CF386 Block Diagram
3 x LVDS Data
(140 to 595 Mbps on Each
LVDS Channel)
100 Q
100 Q
21 x LVCMOS
Outputs
100 Q
LVDS Clock
(20 to 85 MHz)
100 Q
PLL
Receiver Clock Out
PWR DWN
Copyright © 2016, Texas Instruments Incorporated
Figure 19. DS90CF366 Block Diagram
Copyright © 1999–2016, Texas Instruments Incorporated
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