DS90CF366_16 Datasheet, PDF (12/38 Pages) Texas Instruments – DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz

DS90CF366, DS90CF386
SNLS055J – NOVEMBER 1999 – REVISED MAY 2016
Timing Diagrams (continued)
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Figure 5. DS90CF3x6 (Receiver) Setup or Hold and High or Low Times
Figure 6. DS90CF3x6 (Receiver) Clock In to Clock Out Delay
Figure 7. DS90CF3x6 (Receiver) Phase Lock Loop Set Time
RxCLK IN
(Differential)
RxIN3
(Single-Ended)
RxOUT5-1 RxOUT27-1 RxOUT23
RxOUT17
RxOUT16
RxOUT11
RxOUT10
RxOUT5
RxOUT27
RxIN2
(Single-Ended)
RxOUT20-1 RxOUT19-1 RxOUT26
RxOUT25
RxOUT24
RxOUT22
RxOUT21
RxOUT20
RxOUT19
RxIN1
(Single-Ended)
RxOUT9-1 RxOUT8-1
RxOUT18
RxOUT15
RxOUT14
RxOUT13
RxOUT12
RxOUT9
RxOUT8
RxIN0
(Single-Ended)
RxOUT1-1 RxOUT0-1
RxOUT7
RxOUT6
RxOUT4
RxOUT3
RxOUT2
RxOUT1
RxOUT0
Figure 8. DS90CF386 Mapping of 28 LVCMOS Parallel Data to 4D + C LVDS Serialzied Data
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