DS90CF366_16 Datasheet, PDF (21/38 Pages) Texas Instruments – DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz

www.ti.com
DS90CF366, DS90CF386
SNLS055J – NOVEMBER 1999 – REVISED MAY 2016
Typical Applications (continued)
8.2.1 Design Requirements
For this design example, follow the requirements in Table 1.
PARAMETER
Operating frequency
Bit resolution
Bit data mapping
RSKM (Receiver skew margin)
Input termination for RxIN±
RxIN± board trace impedance
LVCMOS outputs
DC power supply coupling capacitors
Table 1. Design Parameters
DESIGN REQUIREMENTS
LVDS clock must be within 20 MHz to 85 MHz.
DS90CF386: No higher than 24 bpp. The maximum supported resolution is 8-bit RGB.
DS90CF366: No higher than 18 bpp. The maximum supported resolution is 6-bit RGB.
Determine the appropriate mapping required by the panel display following the DS90CF386 or
DS90CF366 outputs.
Ensure that there is acceptable margin between Tx pulse position and Rx strobe position.
Inputs require a 100 Ω ± 10% resistor across each LVDS differential pair. Place as close as
possible to IC input pins.
Design differential trace impedance with 100 Ω ±5%
If unused, leave pins floating. Series resistance on each LVCMOS output optional to reduce
reflections from long board traces. If used, 33-Ω series resistance is typical.
Use a 0.1-µF capacitor to minimize power supply noise. Place as close as possible to V_CC
pins.
8.2.2 Detailed Design Procedure
To design with the DS90CF386 or DS90CF366, determine the following:
• Cable Interface
• Bit Resolution and Operating Frequency
• Bit Mapping from Receiver to Endpoint Panel Display
• RSKM Interoperability with Transmitter Pulse Position Margin
8.2.2.1 Cables
A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The
DS90CF366 requires four pairs of signal wires and the DS90CF386 requires five pairs of signal wires. The ideal
cable interface has a constant 100-Ω differential impedance throughout the path. It is also recommended that
cable skew remain below 120 ps (assuming 85 MHz clock rate) to maintain a sufficient data sampling window at
the receiver.
Depending upon the application and data rate, the interconnecting media between Tx and Rx may vary. For
example, for lower data rate (clock rate) and shorter cable lengths (< 2m), the media electrical performance is
less critical. For higher speed or long distance applications, the media's performance becomes more critical.
Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs).
For example, twin-coax cables have been demonstrated at distances as long as five meters and with the
maximum data transfer of 2.38 Gbps (DS90CF366) and 1.785 Gbps (DS90CF386).
8.2.2.2 Bit Resolution and Operating Frequency Compatibility
The bit resolution of the endpoint panel display reveals whether there are enough bits available in the
DS90CF386 or DS90CF366 to output the required data per pixel. The DS90CF386 has 28 parallel LVCMOS
outputs and can therefore provide a bit resolution up to 24 bpp (bits per pixel). In each clock cycle, the remaining
bits are the three control signals (HSync, VSync, DE) and one spare bit. The DS90CF366 has 21 parallel
LVCMOS outputs and can therefore provide a bit resolution up to 18 bpp (bits per pixel). In each clock cycle, the
remaining bits are the three control signals (HSync, VSync, DE).
The number of pixels per frame and the refresh rate of the endpoint panel display indicate the required operating
frequency of the deserializer clock. To determine the required clock frequency, refer to Equation 1.
f_Clk = [H_Active + H_Blank] × [V_Active + V_Blank] × f_Vertical
where
• H_Active = Active Display Horizontal Lines
Copyright © 1999–2016, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: DS90CF366 DS90CF386