DS90CF366_16 Datasheet, PDF (18/38 Pages) Texas Instruments – DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz

DS90CF366, DS90CF386
SNLS055J – NOVEMBER 1999 – REVISED MAY 2016
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7.3 Feature Description
The DS90CF386 and DS90CF366 consist of several key blocks:
• LVDS Receivers
• Phase Locked Loop (PLL)
• Serial LVDS-to-Parallel LVCMOS Converter
• LVCMOS Drivers
7.3.1 LVDS Receivers
There are five differential LVDS inputs to the DS90CF386 and four differential LVDS inputs to the DS90CF366.
For the DS90CF386, four of the LVDS inputs contain serialized data originating from a 28-bit source transmitter.
For the DS90CF366, three of the LVDS inputs contain serialized data originating from a 21-bit source transmitter.
The remaining LVDS input contains the LVDS clock associated with the data pairs.
7.3.1.1 LVDS Input Termination
The DS90CF386 and DS90CF366 require a single 100-Ω terminating resistor across the true and complement
lines on each differential pair of the receiver input. To prevent reflections due to stubs, this resistor should be
placed as close to the device input pins as possible. Figure 20 shows an example.
Figure 20. LVDS Serialized Link Termination
7.3.2 Phase Locked Loop (PLL)
The FPD Link I devices use an internal PLL to recover the clock transmitted across the LVDS interface. The
recovered clock is then used as a reference to determine the sampling position of the seven serial bits received
per clock cycle. The width of each bit in the serialized LVDS data stream is one-seventh the clock period.
Differential skew (Δt within one differential pair), interconnect skew (Δt of one differential pair to another), and
clock jitter will all reduce the available window for sampling the LVDS serial data streams. Individual bypassing of
each V_CC to ground will minimize the noise passed on to the PLL, thus creating a low jitter LVDS clock to
improve the overall jitter budget.
7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
After the PLL locks to the incoming LVDS clock, the receiver deserializes each LVDS differential data pair into
seven parallel LVCMOS data outputs per clock cycle. For the DS90CF386, the LVDS data inputs map to
LVCMOS outputs according to Figure 8. For the DS90CF366, the LVDS data inputs map to LVCMOS outputs
according to Figure 9.
7.3.4 LVCMOS Drivers
The LVCMOS outputs from the DS90CF386 and DS90CF366 are the deserialized parallel single-ended data
from the serialized LVDS differential data pairs. Each LVCMOS output is clocked by the PLL and strobes on the
RxCLKOUT falling edge. All unused DS90CF386 and DS90CF366 RxOUT outputs can be left floating.
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