DS90CF366_16 Datasheet, PDF (24/38 Pages) Texas Instruments – DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz

DS90CF366, DS90CF386
SNLS055J – NOVEMBER 1999 – REVISED MAY 2016
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In the case where either DS90CF386 or DS90CF366 is used to support 18 bpp, Table 2 is commonly used,
where RxIN3± (if applicable) is left as No Connect. With this mapping, MSBs of RGB data are retained on
RXIN0±, RXIN1±, and RXIN2± while the two LSBs for the original 8-bit RGB resolution are ignored from RxIN3±.
8.2.2.4 RSKM Interoperability
One of the most important factors when designing the receiver into a system application is assessing how much
RSKM (Receiver Skew Margin) is available. In each LVDS clock cycle, the LVDS data stream carries seven
serialized data bits. Ideally, the Transmit Pulse Position for each bit will occur every (n × T)/7 seconds, where
n = Bit Position and T = LVDS Clock Period. Likewise, ideally the Rx Strobe Position for each bit will occur every
((n + 0.5) × T)/7 seconds. However, in real systems, both LVDS Tx and Rx will have non-ideal pulse and strobe
position for each bit position due to the effects of cable skew, clock jitter, and ISI. This concept is illustrated in
Figure 23.
Rspos0
min
max
Rspos1
min
max
Tppos0 Bit 0 Left Margin
min
max
Ideal Rx Strobe
Bit 0 Right Margin Tppos1 Bit 1 Left Margin
min
max
Position
Bit0
Bit 1 Right Margin Tppos2
Ideal Rx Strobe
min
max
Position
Bit1
Figure 23. RSKM Measurement Example
All left and right margins for Bits 0-6 must be considered in order to determine the absolute minimum for the
whole LVDS bit stream. This absolute minimum corresponds to the RSKM.
To improve RSKM performance between LVDS transmitter and receiver, designers often either advance or delay
the LVDS clock compared to the LVDS data. Moving the LVDS clock compared to the LVDS data can improve
the location of the setup and hold time for the transmitter compared to the setup and hold time for the receiver.
If there is less left bit margin than right bit margin, the LVDS clock can be delayed so that the Rx strobe position
for incoming data appears to be delayed. If there is less right bit margin than left bit margin, all the LVDS data
pairs can be delayed uniformly so that the LVDS clock and Rx strobe position for incoming data appear to
advance. To delay an LVDS data or clock pair, designers either add more PCB trace length or install a capacitor
between the LVDS transmitter and receiver. It is important to note that when using these techniques, all
serialized bit positions are shifted right or left uniformly.
When designing the DS90CF386 or DS90CF366 receiver with a third-party OpenLDI transmitter, users must
calculate the skew margin budget (RSKM) based on the Tx pulse position and the Rx strobe position to ensure
error-free transmission. For more information about calculating RSKM, refer to Application Note, Receiver Skew
Margin for Channel Link I and FPD Link I Devices (SNLA249).
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