DS90CF366_16 Datasheet, PDF (15/38 Pages) Texas Instruments – DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz

www.ti.com
Timing Diagrams (continued)
DS90CF366, DS90CF386
SNLS055J – NOVEMBER 1999 – REVISED MAY 2016
Figure 12. DS90CF366 (Receiver) LVDS Input Strobe Position
C: Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos: Transmitter output pulse position (min and max)
Cable skew: Typically 10 ps–40 ps per foot, media dependent
RSKM = Cable skew (type, length) + source clock jitter (cycle-to-cycle)⁽¹⁾ + ISI (inter-symbol interference)⁽²⁾
(1) Cycle-to-cycle jitter depends on the Tx source. Clock jitter should be maintained to less than 250 ps at 85 MHz.
(2) ISI is dependent on interconnect length; may be zero.
Figure 13. Receiver LVDS Input Skew Margin
Copyright © 1999–2016, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: DS90CF366 DS90CF386