AM1705_15 Datasheet, PDF (94/165 Pages) Texas Instruments – AM1705 ARM® Microprocessor

AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
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6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
Table 6-46 and Table 6-47 assume testing over recommended operating conditions (see Figure 6-29 and
Figure 6-30).
Table 6-46. McASP1 Timing Requirements^{(1) (2)}
No.
PARAMETER
1 t_c(AHCLKRX)
Cycle time, AHCLKR1 external, AHCLKR1 input
Cycle time, AHCLKX1 external, AHCLKX1 input
2 t_w(AHCLKRX)
Pulse duration, AHCLKR1 external, AHCLKR1 input
Pulse duration, AHCLKX1 external, AHCLKX1 input
3 t_c(ACLKRX)
Cycle time, ACLKR1 external, ACLKR1 input
Cycle time, ACLKX1 external, ACLKX1 input
4 t_w(ACLKRX)
Pulse duration, ACLKR1 external, ACLKR1 input
Pulse duration, ACLKX1 external, ACLKX1 input
Setup time, AFSR1 input to ACLKR1 internal⁽³⁾
Setup time, AFSX1 input to ACLKX1 internal
Setup time, AFSR1 input to ACLKR1 external input⁽³⁾
5 t_{su(AFSRX-ACLKRX) Setup time, AFSX1 input to ACLKX1 external input}
Setup time, AFSR1 input to ACLKR1 external output⁽³⁾
Setup time, AFSX1 input to ACLKX1 external output
Hold time, AFSR1 input after ACLKR1 internal⁽³⁾
Hold time, AFSX1 input after ACLKX1 internal
Hold time, AFSR1 input after ACLKR1 external input⁽³⁾
6 t_{h(ACLKRX-AFSRX) Hold time, AFSX1 input after ACLKX1 external input}
Hold time, AFSR1 input after ACLKR1 external output⁽³⁾
7
t_{su(AXR-ACLKRX)}
8
t_{h(ACLKRX-AXR)}
Hold time, AFSX1 input after ACLKX1 external output
Setup time, AXR1[n] input to ACLKR1 internal ⁽³⁾
Setup time, AXR1[n] input to ACLKX1 internal⁽⁴⁾
Setup time, AXR1[n] input to ACLKR1 external input⁽³⁾
Setup time, AXR1[n] input to ACLKX1 external input ⁽⁴⁾
Setup time, AXR1[n] input to ACLKR1 external output⁽³⁾
Setup time, AXR1[n] input to ACLKX1 external output ⁽⁴⁾
Hold time, AXR1[n] input after ACLKR1 internal⁽³⁾
Hold time, AXR1[n] input after ACLKX1 internal⁽⁴⁾
Hold time, AXR1[n] input after ACLKR1 external input⁽³⁾
Hold time, AXR1[n] input after ACLKX1 external input ⁽⁴⁾
Hold time, AXR1[n] input after ACLKR1 external output⁽³⁾
Hold time, AXR1[n] input after ACLKX1 external output ⁽⁴⁾
MIN
25
25
12.5
12.5
greater of 2P or 25
greater of 2P or 25
12.5
12.5
10.4
10.4
2.6
2.6
2.6
2.6
-1.9
-1.9
0.7
0.7
0.7
0.7
10.4
10.4
2.6
2.6
2.6
2.6
-1.8
-1.8
0.5
0.5
0.5
0.5
(1) ACLKX1 internal – McASP1 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX1 external input – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX1 external output – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR1 internal – McASP1 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR1 external input – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR1 external output – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
(4) McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
94
Peripheral Information and Electrical Specifications
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