AM1705_15 Datasheet, PDF (61/165 Pages) Texas Instruments – AM1705 ARM® Microprocessor

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AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
6.10 External Memory Interface A (EMIFA)
EMIFA is one of two external memory interfaces supported on the device. It supports asynchronous
memory types, such as NAND and NOR flash and Asynchronous SRAM.
6.10.1 EMIFA Asynchronous Memory Support
EMIFA supports asynchronous:
• SRAM memories
• NAND Flash memories
• NOR Flash memories
The device supports up to 13 address lines and an external wait/interrupt input. Up to 2 asynchronous
chip selects are supported by EMIFA (EMA_CS[3:2]) .
Each chip select has the following individually programmable attributes:
• Data Bus Width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turn around time
• Extended Wait Option With Programmable Timeout
• Select Strobe Option
• NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.
6.10.2 EMIFA Connection Examples
A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 6-12.
This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the
EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND
area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions
selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to
bootload it.
EMIFA
EMA_A[1]
EMA_A[2]
EMA_D[7:0]
EMA_CS[2]
EMA_CS[3]
EMA_WE
EMA_OE
EMA_WAIT
D_VDD
EMA_CS[4]
EMA_CS[5]
ALE
CLE
DQ[7:0]
CE1
CE2
WE
RE
R/B1
R/B2
NAND
FLASH
x8,
MultiPlane
ALE
CLE
DQ[7:0]
CE1
CE2
WE
RE
R/B1
R/B2
NAND
FLASH
x8,
MultiPlane
Figure 6-12. AM1705 EMIFA Connection Diagram: Multiple NAND Flash Planes
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Peripheral Information and Electrical Specifications
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