AM1705_15 Datasheet, PDF (1/165 Pages) Texas Instruments – AM1705 ARM® Microprocessor

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AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
AM1705 ARM® Microprocessor
1 AM1705 ARM Microprocessor
1.1 Features
1
• 375- and 456-MHz ARM926EJ-S™ RISC Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– Single-Cycle MAC
– ARM Jazelle® Technology
– Embedded ICE-RT™ for Real-Time Debug
• ARM9™ Memory Architecture
– 16KB of Instruction Cache
– 16KB of Data Cache
– 8KB of RAM (Vector Table)
– 64KB of ROM
• Enhanced Direct Memory Access Controller 3
(EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
• 128KB of RAM Memory
• 3.3-V LVCMOS I/Os (Except for USB Interface)
• Two External Memory Interfaces:
– EMIFA
• NOR (8-Bit-Wide Data)
• NAND (8-Bit-Wide Data)
– EMIFB
• 16-Bit SDRAM with 128-MB Address Space
• Three Configurable 16550-Type UART Modules:
– UART0 with Modem Control Signals
– 16-Byte FIFO
– 16x or 13x Oversampling Option
– Autoflow Control Signals (CTS, RTS) on UART0
Only
• Two Serial Peripheral Interfaces (SPIs) Each with
One Chip Select
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Real-Time Unit
(PRU) Cores
• 32-Bit Load-Store RISC Architecture
• 4KB of Instruction RAM per Core
• 512 Bytes of Data RAM per Core
• PRUSS can be Disabled via Software to
Save Power
– Standard Power-Management Mechanism
• Clock Gating
• Entire Subsystem Under a Single PSC Clock
Gating Domain
1
– Dedicated Interrupt Controller
– Dedicated Switched Central Resource
• Multimedia Card (MMC)/Secure Digital (SD) Card
Interface with Secure Data I/O (SDIO)
• Two Master and Slave Inter-Integrated Circuit (I²C
Bus™)
• USB 2.0 OTG Port with Integrated PHY (USB0)
– USB 2.0 Full-Speed Client
– USB 2.0 Full- and Low-Speed Host
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) RX and TX
• Two Multichannel Audio Serial Ports (McASPs):
– Six Clock Zones and 28 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
– RMII Media-Independent Interface
– Management Data I/O (MDIO) Module
• One 64-Bit General-Purpose Timer (Configurable
as Two 32-Bit Timers)
• One 64-Bit General-Purpose Watchdog Timer
(Configurable as Two 32-Bit General-Purpose
Timers)
• Three Enhanced Pulse Width Modulators
(eHRPWMs):
– Dedicated 16-Bit Time-Base Counter with
Period and Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric, or 3
Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules:
– Configurable as 3 Capture Inputs or 3 Auxiliary
Pulse Width Modulator (APWM) Outputs
– Single-Shot Capture of up to Four Event Time-
Stamps
• Two 32-Bit Enhanced Quadrature Encoder Pulse
(eQEP) Modules
• 176-pin PowerPAD™ Plastic Quad Flat Pack [PTP
suffix], 0.5-mm Pin Pitch
• Commercial, Industrial, or Extended Temperature
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.