AM1705_15 Datasheet, PDF (72/165 Pages) Texas Instruments – AM1705 ARM® Microprocessor

AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
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Table 6-25. EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive
Temperature Ranges (continued)
NO.
PARAMETER
CVDD = 1.3 V⁽¹⁾
MIN
MAX
CVDD = 1.2V⁽²⁾ _UNI
MIN
MAX ^T
5 t_d(CLKH-DQMV)
6 t_{oh(CLKH-DQMIV)}
Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid
Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0]
invalid
4.25
5.1 ns
1.1
0.9
ns
7 t_d(CLKH-AV)
Delay time, EMB_CLK rising to EMB_A[12:0] and
EMB_BA[1:0] valid
4.25
5.1 ns
8 t_oh(CLKH-AIV)
Output hold time, EMB_CLK rising to EMB_A[12:0] and
EMB_BA[1:0] invalid
1.1
0.9
ns
9 t_d(CLKH-DV)
10 t_oh(CLKH-DIV)
11 t_d(CLKH-RASV)
12 t_{oh(CLKH-RASIV)}
13 t_d(CLKH-CASV)
14 t_{oh(CLKH-CASIV)}
15 t_d(CLKH-WEV)
16 t_{oh(CLKH-WEIV)}
17 t_{dis(CLKH-DHZ)}
18 t_(CLKH-DLZ)
Delay time, EMB_CLK rising to EMB_D[31:0] valid
Output hold time, EMB_CLK rising to EMB_D[31:0] invalid
Delay time, EMB_CLK rising to EMB_RAS valid
Output hold time, EMB_CLK rising to EMB_RAS invalid
Delay time, EMB_CLK rising to EMB_CAS valid
Output hold time, EMB_CLK rising to EMB_CAS invalid
Delay time, EMB_CLK rising to EMB_WE valid
Output hold time, EMB_CLK rising to EMB_WE invalid
Delay time, EMB_CLK rising to EMB_D[31:0] tri-stated
Output hold time, EMB_CLK rising to EMB_D[31:0] driving
4.25
5.1 ns
1.1
0.9
ns
4.25
5.1 ns
1.1
0.9
ns
4.25
5.1 ns
1.1
0.9
ns
4.25
5.1 ns
1.1
0.9
ns
4.25
5.1 ns
1.1
0.9
ns
EMB_CLK
EMB_CS[0]
EMB_WE_DQM[3:0]
EMB_BA[1:0]
EMB_A[12:0]
EMB_D[31:0]
EMB_RAS
EMB_CAS
EMB_WE
BASIC SDRAM
WRITE OPERATION
1
22
3
4
5
6
7
8
7
8
9
10
11
12
13
15
16
Figure 6-19. EMIFB Basic SDRAM Write Operation
72
Peripheral Information and Electrical Specifications
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