AM1705_15 Datasheet, PDF (68/165 Pages) Texas Instruments – AM1705 ARM® Microprocessor

AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
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6.11.2 Interfacing to SDRAM
The EMIFB supports a glueless interface to SDRAM devices with the following characteristics:
• Pre-charge bit is A[10]
• Supports 8, 9, 10 or 11 column address bits
• Supports up to 13 row address bits
• Supports 1, 2 or 4 internal banks
Table 6-20 shows the supported SDRAM configurations for EMIFB.
Table 6-20. EMIFB Supported SDRAM Configurations⁽¹⁾
SDRAM
Memory
Data Bus
Width
(bits)
Number of EMIFB Data
Memories Bus Size
Rows
Columns
Banks
Total Memory
(Mbits)
Total Memory
(Mbytes)
Memory
Density
(Mbits)
1
16
13
8
1
32
4
32
1
16
13
8
2
64
8
64
1
16
13
8
4
128
16
128
1
16
13
9
1
64
8
64
1
16
13
9
2
128
16
128
1
16
13
9
4
16
1
16
13
10
1
256
32
256
128
16
128
1
16
13
10
2
256
32
256
1
16
13
10
4
512
64
512
1
16
13
11
1
256
32
256
1
16
13
11
2
512
64
512
1
16
13
11
4
1024
128
1024
2
16
13
8
1
32
4
16
2
16
13
8
2
64
8
32
2
16
13
8
4
128
16
64
2
16
13
9
1
64
8
32
2
16
13
9
2
128
16
64
2
16
13
9
4
8
2
16
13
10
1
256
32
128
128
16
64
2
16
13
10
2
256
32
128
2
16
13
10
4
512
64
256
2
16
13
11
1
256
32
128
2
16
13
11
2
512
64
256
2
16
13
11
4
1024
128
512
(1) The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
68
Peripheral Information and Electrical Specifications
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