AM1705_15 Datasheet, PDF (63/165 Pages) Texas Instruments – AM1705 ARM® Microprocessor

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AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
6.10.4 EMIFA Electrical Data/Timing
The following assume testing over recommended operating conditions.
Table 6-18. EMIFA Asynchronous Memory Timing Requirements⁽¹⁾
No. PARAMETER
MIN NOM MAX UNIT
READS and WRITES
E t_c(CLK)
2 t_{w(EM_WAIT)}
Cycle time, EMIFA module clock
Pulse duration, EM_WAIT assertion and deassertion
READS
10
ns
2E
ns
12 t_{su(EMDV-EMOEH)}
Setup time, EM_D[15:0] valid before EM_OE high
3
ns
13 t_{h(EMOEH-EMDIV)}
Hold time, EM_D[15:0] valid after EM_OE high
0
ns
14 t_{su (EMOEL-EMWAIT)}
Setup Time, EM_WAIT asserted before end of Strobe Phase⁽²⁾
4E+3
ns
WRITES
28 t_{su (EMWEL-EMWAIT)}
Setup Time, EM_WAIT asserted before end of Strobe Phase⁽²⁾
4E+3
ns
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-15 and Figure 6-16 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 6-19. EMIFA Asynchronous Memory Switching Characteristics^{(1) (2) (3)}
No.
PARAMETER
MIN
NOM
MAX
UNIT
READS and WRITES
1 t_{d(TURNAROUND)} Turn around time
READS
(TA)*E - 3
(TA)*E
(TA)*E + 3 ns
3
t_c(EMRCYCLE)
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
(RS+RST+RH)*E
-3
(RS+RST+RH)*E
(RS+RST+RH)*E
+3
ns
(RS+RST+RH+E (RS+RST+RH+EWC (RS+RST+RH+E
WC)*E - 3
)*E
WC)*E + 3
ns
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 0)
4 t_{su(EMCEL-EMOEL) Output setup time, EMA_CE[5:2] low to}
EMA_OE low (SS = 1)
(RS)*E-3
-3
(RS)*E
0
(RS)*E+3 ns
+3 ns
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 0)
5 t_{h(EMOEH-EMCEH) Output hold time, EMA_OE high to}
EMA_CE[5:2] high (SS = 1)
(RH)*E - 3
-3
(RH)*E
0
(RH)*E + 3 ns
+3 ns
6
t_{su(EMBAV-EMOEL)}
Output setup time, EMA_BA[1:0] valid to
EMA_OE low
(RS)*E-3
(RS)*E
(RS)*E+3 ns
7
t_{h(EMOEH-EMBAIV)}
Output hold time, EMA_OE high to
EMA_BA[1:0] invalid
(RH)*E-3
(RH)*E
(RH)*E+3 ns
8
t_{su(EMBAV-EMOEL)}
Output setup time, EMA_A[13:0] valid to
EMA_OE low
(RS)*E-3
(RS)*E
(RS)*E+3 ns
9
t_{h(EMOEH-EMAIV)}
Output hold time, EMA_OE high to
EMA_A[13:0] invalid
(RH)*E-3
(RH)*E
(RH)*E+3 ns
10 t_w(EMOEL)
EMA_OE active low width (EW = 0)
EMA_OE active low width (EW = 1)
(RST)*E-3
(RST+EWC)*E-3
(RST)*E
(RST)*E+3 ns
(RST+EWC)*E
(RST+EWC)*E+
3
ns
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256].
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
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Peripheral Information and Electrical Specifications
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