AM1705_15 Datasheet, PDF (103/165 Pages) Texas Instruments – AM1705 ARM® Microprocessor

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AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
Table 6-51. Additional⁽¹⁾ SPI0 Master Timings, 4-Pin Enable Option^{(2) (3)}
No.
17 t_{d(ENA_SPC)M}
18 t_{d(SPC_ENA)M}
PARAMETER
MIN
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Delay from slave assertion of
SPI0_ENA active to first SPI0_CLK
from master.⁽⁴⁾
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Max delay for slave to deassert
SPI0_ENA after final SPI0_CLK edge
to ensure master does not begin the
next transfer.⁽⁵⁾
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
MAX
UNIT
3P + 3.6
0.5t_c(SPC)M + 3P + 3.6
ns
3P + 3.6
0.5t_c(SPC)M + 3P + 3.6
0.5t_c(SPC)M + P + 5
P+5
ns
0.5t_c(SPC)M + P + 5
P+5
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-49).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
Table 6-52. Additional⁽¹⁾ SPI0 Master Timings, 4-Pin Chip Select Option^{(2) (3)}
No.
19 t_{d(SCS_SPC)M}
20 t_{d(SPC_SCS)M}
PARAMETER
Delay from SPI0_SCS active to first
SPI0_CLK^{(4) (5)}
Delay from final SPI0_CLK edge to
master deasserting SPI0_SCS ^{(6) (7)}
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
MIN
MAX UNIT
2P - 5
0.5t_c(SPC)M + 2P - 5
ns
2P - 5
0.5t_c(SPC)M + 2P - 5
0.5t_c(SPC)M + P - 3
P-3
ns
0.5t_c(SPC)M + P - 3
P-3
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-49).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Peripheral Information and Electrical Specifications 103
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